參數(shù)資料
型號(hào): M30220FCGP
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁(yè)數(shù): 80/161頁(yè)
文件大?。?/td> 0K
代理商: M30220FCGP
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Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Stop Mode, Wait Mode
25
Table 1.9.3. Port status during wait mode
Pin
Status
Port
Retains status before wait mode
CKOUT
When fC1 selected
Does not stop
When f1, clock devided counter output selected
Retains status before stop mode
Does not stop when the WAIT peripheral
function clock stop bit is “0”.
When the WAIT peripheral function clock
stop bit is “1”, the status immediately prior
to entering wait mode is main-tained.
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC132,
fC1, and fC32 do not stop so that the peripherals using fC132, fC1, and fC32 do not contribute to the power
saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with
this bit set to “1”. Table 1.9.3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel wait mode,
that interrupt must first have been enabled. If an interrupt is used to cancel wait mode, the microcomputer
restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruc-
tion was executed.
Pin
Status
Port
Retains status before stop mode
CKOUT
When fC1 selected
“H”
When f1, clock devided counter output selected
Retains status before stop mode
Table 1.9.2. Port status during stop mode
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation , BCLK, f1 to f32, fC, fC132, fC1, fC32 and fAD stops in stop mode, peripheral functions
such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate
provided that the event counter mode is set to an external pulse, and UART0 to UART2 functions provided
an external clock is selected. Table 1.9.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
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