
10.8 TOU (Output-Related 24-Bit Timer)
MULTIJUNCTION TIMERS
10
10-166
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
10.8.10 PWMOFF Input Processing Control Registers
PWMOFF0 Input Processing Control Register (PWMOFF0CR)
<Address: H'0080 07E0>
<Upon exiting reset: H’00>
b
Bit Name
Function
R
W
0–3
No function assigned. Fix to "0."
00
4
PWMOFF0SP
–
0
W
PWMOFF0S write control bit
5–7
PWMOFF0S
000: Input has no effect
R
W
PWMOFF0 input processing control bit
001: Rising edge
010: Falling edge
011: Both edges
10X: "L" level
11X: "H" level
PWMOFF1 Input Processing Control Register (PWMOFF1CR)
<Address: H'0080 0BE0>
<Upon exiting reset: H’00>
b
Bit Name
Function
R
W
0–3
No function assigned. Fix to "0."
00
4
PWMOFF1SP
–
0
W
PWMOFF1S write control bit
5–7
PWMOFF1S
000: Input has no effect
R
W
PWMOFF1 input processing control bit
001: Rising edge
010: Falling edge
011: Both edges
10X: "L" level
11X: "H" level
The PWMOFF input processing control registers are used to set the active edge or level entered for PWM
output disable control from an external pin. For details about the PWM output disable function, see Section
10.8.20, “PWM Output Disable Function.”
To set the PWMOFF input processing control bits, follow the procedure described below.
1. Write data ‘1’ to the PWMOFFnS write control bit (PWMOFFnSP).
2. After 1 above, write data ‘0’ to the PWMOFFnS write control bit (PWMOFFnSP) and the set value to the
PWMOFF input processing control bits (PWMOFFnS).
Note: If theare are Writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2,
the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the
writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting.
However the writing cycle from RTD and DRI are not effected.
b0
12
3456
b7
PWMOFF0SP
PWMOFF0S
000
0000
0
b0
12
3456
b7
PWMOFF1SP
PWMOFF1S
000
0000
0