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型號(hào)：	M32185F4VFP
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁(yè)數(shù)：	517/1032頁(yè)
文件大?。?/td>	5750K
代理商：	M32185F4VFP

A/D CONVERTER

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

11.3.2 A/D Conversion by Successive Approximation Method

The A/D Converter use an A/D conversion start trigger (software or hardware) as they start A/D conver-

sion. Once A/D conversion begins, the following operation is automatically performed.

1. During single mode, A/D Single Mode Register 0’s A/D conversion/comparate completion bit is cleared

to "0." During scan mode, A/D Scan Mode Register 0’s A/D conversion completion bit is cleared to "0."

2. The content of the A/D Successive Approximation Register is cleared to H’0000.

3. The A/D Successive Approximation Register’s most significant bit (bit 6) is set to "1."

4. The comparison voltage, Vref (Note 1), is fed from the D/A Converter into the comparator.

5. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, and the comparison

result will be stored in bit 6.

If Vref < VIN, then bit 6 = "1"

If Vref > VIN, then bit 6 = "0"

6. Operations in 3 through 5 above are executed for all other bits from bit 7 to bit 15.

7. The value stored in the A/D Successive Approximation Register by the time comparison for bit 15 has

finished is held in it as the A/D conversion result.

11.3 Functional Description of A/D Converter

1st comparison

2nd comparison

3rd comparison

10th comparison

Result of 1st comparison

Result of 2nd comparison

If Vref > VIN, then nX = 0

If Vref < VIN, then nX = 1

A/D Successive Approximation Register (ADiSAR)

Figure 11.3.2 Changes of the A/D Successive Approximation Register during A/D Convert Operation

Note 1: The comparison voltage, Vref (the voltage fed from the D/A Converter into the comparator), is

determined according to changes of the A/D Successive Approximation Register content. Shown

below are the equations used to calculate the comparison voltage, Vref.

If the A/D Successive Approximation Register content = 0

Vref [V] = 0

If the A/D Successive Approximation Register content = 1 to 1,023

Vref [V] = (reference voltage VREF0 /1,024)

× (A/D Successive Approximation Register content – 0.5)

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