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參數(shù)資料
| 型號(hào)： | M34282 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 4 Bits CMOS Microcomputer(4位單片機(jī)) |
| 中文描述： | 4位單片微機(jī)的CMOS（4位單片機(jī)） |
| 文件頁(yè)數(shù)： | 19/70頁(yè) |
| 文件大小： | 560K |
| 代理商： | M34282 |
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MITSUBISHI
ELECTRIC
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
19
MITSUBISHI MICROCOMPUTERS
4282 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RAM BACK-UP MODE
The 4282 Group has the RAM back-up mode.
When the POF instruction is executed, system enters the RAM
back-up state.
As oscillation stops retaining RAM, the functions and states of
reset circuit at RAM back-up mode, power dissipation can be
reduced without losing the contents of RAM. Table 7 shows the
function and states retained at RAM back-up. Figure 22 shows
the state transition.
(1) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up state by executing the POF
instruction, the CPU starts executing the software from address
0 in page 0. In this case, the P flag is
“
1.
”
(2) Cold start condition
The CPU starts executing the software from address 0 in page
0 when any of the following conditions is satisfied .
reset by power-on reset circuit is performed
reset by watchdog timer is performed
reset by voltage drop detection circuit is performed
In this case, the P flag is
“
0.
”
(3) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
Table 7 Functions and states retained at RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port CARR
Ports D
0
–
D
7
Ports E
0
, E
1
Port G
Timer control registers V1, V2
Pull-down control registers PU0, PU1
Logic operation selection register LO
Timer 1 function, Timer 2 function
Timer underflow flags (T1F, T2F)
Watchdog timer (WDT)
Watchdog timer flags (WDF1, WDF2)
Most significant ROMcode reference enable flag (URS)
Notes 1:
“
O
”
represents that the function can be retained, and
“
”
represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2:The stack pointer (SP) points the level of the stack
register and is initialized to
“
11
2
”
at RAM back-up.
RAM back-up
O
O
O
O
O
Fig. 22 State transition
Fig. 23 Set source and clear source of the P flag
Fig. 24 Start condition identified example using the SNZP
instruction
: Microcomputer starts its operation after f(X
IN
) is counted to16384 times.
Stabilizing time a
POF instruction
is executed
A
f(X
IN
) oscillation
Return input
(Stabilizing time a )
B
(RAM back-up
mode)
f(X
IN
) stop
Reset
(Stabilizing time a )
S
R
Q
Power down flag P
POF instruction
Reset input
G
Set source POF instruction is executed
G
Clear source Reset input
Software start
P =
“
1
”
Yes
Warm start
Cold start
No
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