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參數(shù)資料
| 型號： | M34282 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 4 Bits CMOS Microcomputer(4位單片機) |
| 中文描述： | 4位單片微機的CMOS（4位單片機） |
| 文件頁數(shù)： | 62/70頁 |
| 文件大小： | 560K |
| 代理商： | M34282 |
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MITSUBISHI
ELECTRIC
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
62
MITSUBISHI MICROCOMPUTERS
4282 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Number of transfer
Command
Read
Program
Program verify
In the first transfer, the command code is input. Then, address
input or data input/output is performed according to the
contents of the command code. Table 11 shows the software
command used in the PROM mode. The following explains
each software command.
(2) Functional outline
In the PROM mode, data is transferred with the clock-
synchronous serial input/output. The input data is read through
the SDA pin into the internal circuit synchronously with the
rising edge of the serial clock pulse. The output data is output
from the SDA pin synchronously with the falling edge of the
serial clock pulse. Data is transferred in units of 8 bits.
Table 11 Software command
First command
code input
15
16
25
16
35
16
Second
Read address L (input)
Program address L (input)
Program address L (input)
Fourth
Read data L (output)
Program data L (input)
Program data L (input)
Third
Read address H (input)
Program address H (input)
Program address H (input)
Number of transfer
Command
Read
Program
Program verify
Fifth
Read data H (output)
Program data H (input)
Program data H (input)
Seventh
Verify data H (output)
Sixth
Verify data L (output)
(3) Read
Input the command code 15
16
in the first transfer. Proceed
and input the low-order 8 bits and the high-order 8 bits of the
address and pull the PGM pin to
“
L.
”
When this is done, the
contents of input address is read and stored into the internal
data latch.
When the PGM pin is released back to
“
H
”
and serial clock is
input to the SCLK pin, the low-order 8 bits and high-order 8
bits of read data which have been stored into the data latch,
are serially output from the SDA pin.
Note: When outputting the read data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is
placed in the high-impedance state during the th
(C
–
E)
period after the last rising edge of the serial clock (at the 16th bit).
Fig. 29 Timing at reading
t
CR
t
RC
1 0 1 0 1 0 0 0
Command code input (15
16
)
A0
A7
Read address input (L)
Read address input (H)
SCLK
SDA
PGM
Read
t
WR
t
CH
D0
D7
Read data output (L)
t
CH
D8
Read data output (H)
t
CH
0 0 0 0 0 0 0
A8A9
0 0 0 0 0
A10
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