參數(shù)資料
型號: M36DR432-ZAT
廠商: 意法半導體
英文描述: 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
中文描述: 32兆位的2Mb x16插槽,雙行,頁閃存和4兆位256K x16的SRAM,多個存儲產(chǎn)品
文件頁數(shù): 31/52頁
文件大?。?/td> 834K
代理商: M36DR432-ZAT
31/52
M36DR432AD, M36DR432BD
Table 18. Flash Read AC Characteristics
Note: 1. Sampled only, not 100% tested.
2. GF may be delayed by up to t
ELQV
- t
GLQV
after the falling edge of EF without increasing t
ELQV
.
3. To be characterized.
Symbol
Alt
Parameter
Test Condition
M36DR432AD, M36DR432BD
Unit
85
100
120
Min
Max
Min
Max
Min
Max
t
AVAV
t
RC
Address Valid to Next
Address Valid
EF = V
IL
, GF = V
IL
85
(3)
100
120
ns
t
AVQV
t
ACC
Address Valid to
Output Valid (Random)
EF = V
IL
, GF = V
IL
85
(3)
100
120
ns
t
AVQV1
t
PAGE
Address Valid to
Output Valid (Page)
EF = V
IL
, GF = V
IL
30
(3)
35
45
ns
t
ELQX
(1)
t
LZ
Chip Enable Low to
Output Transition
GF = V
IL
0
0
0
ns
t
ELQV
(2)
t
CE
Chip Enable Low to
Output Valid
GF = V
IL
85
(3)
100
120
ns
t
GLQX
(1)
t
OLZ
Output Enable Low to
Output Transition
EF = V
IL
0
0
0
ns
t
GLQV
(2)
t
OE
Output Enable Low to
Output Valid
EF = V
IL
25
(3)
25
35
ns
t
EHQX
t
OH
Chip Enable High to
Output Transition
GF = V
IL
0
0
0
ns
t
EHQZ
(1)
t
HZ
Chip Enable High to
Output Hi-Z
GF = V
IL
20
(3)
25
35
ns
t
GHQX
t
OH
Output Enable High to
Output Transition
EF = V
IL
0
0
0
ns
t
GHQZ
(1)
t
DF
Output Enable High to
Output Hi-Z
EF = V
IL
20
(3)
25
35
ns
t
AXQX
t
OH
Address Transition to
Output Transition
EF = V
IL
, GF = V
IL
0
0
0
ns
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M36DR432A100ZA6T 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
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