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參數(shù)資料
| 型號： | M36DR432C |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| 中文描述： | 32兆位的2Mb x16插槽，雙行，頁閃存和4兆位256K x16的SRAM，多個存儲產(chǎn)品 |
| 文件頁數(shù)： | 22/46頁 |
| 文件大?。?/td> | 330K |
| 代理商： | M36DR432C |
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M36DR432C, M36DR432D
22/46
SRAM COMPONENT
Device Operations
The following operations can be performed using
the appropriate bus cycles: Read Array, Write Ar-
ray, Output Disable, Power Down (see Table 3).
Read.
Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (WS) is at V
IH
with
Output Enable (GS) at V
IL
, and both Chip Enables
(E1S and E2S) and UBS, LBS combinations are
asserted.
Valid data will be available at the output pins within
t
AVQV
after the last stable address, providing GS is
Low, E1S is Low and E2S is High. If Chip Enable
or Output Enable access times are not met, data
access will be measured from the limiting parame-
ter (t
E1LQV
, t
E2HQV
, or t
GLQV
) rather than the ad-
dress. Data out may be indeterminate at t
E1LQX
,
t
E2HQX
and t
GLQX
, but data lines will always be val-
id at t
AVQV
(see Table 31, Figures 16 and 17).
Write.
Write operations are used to write data in
the SRAM. The SRAM is in Write mode whenever
the WS and E1S pins are at V
IL
, with E2S at V
IH
.
Either the Chip Enable inputs (E1S and E2S) or
the Write Enable input (WS) must be de-asserted
during address transitions for subsequent write cy-
cles. Write begins with the concurrence of both
Chip Enables being active with WS at V
IL
. A Write
begins at the latest transition among E1S going to
V
IL
, E2S going to V
IH
and WS going to V
IL
. There-
fore, address setup time is referenced to Write En-
able and both Chip Enables as t
AVWL
, t
AVE1L
and
t
AVE2H
respectively, and is determined by the latter
occurring edge. The Write cycle can be terminated
by the rising edge of E1S, the rising edge of WS or
the falling edge of E2S, whichever occurs first.
If the Output is enabled (E1S=V
IL
, E2S=V
IH
and
GS=V
IL
), then WS will return the outputs to high
impedance within t
WLQZ
of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for t
DVWH
before the rising edge of Write Enable, or for
t
DVE1H
before the rising edge of E1S or for t
DVE2L
before the falling edge of E2S, whichever occurs
first, and remain valid for t
WHDX
, t
E1HAX
or t
E2LAX
(see Table 32, Figure 19, 21, 23).
Standby/Power-Down.
The SRAM chip has a
Chip Enable power-down feature which invokes
an automatic standby mode (see Table 31, Figure
18) whenever either Chip Enable is de-asserted
(E1S=V
IH
or E2S=V
IL
).
Data Retention
The SRAM data retention performances as V
DDS
go down to V
DR
are described in Table 33 and Fig-
ure 23, 24. In E1S controlled data retention mode,
minimum standby current mode is entered when
E1S
≥
V
DDS
– 0.2V
and
E2S
≥
V
DDS
– 0.2V. In E2S controlled data reten-
tion mode, minimum standby current mode is en-
tered when E2S
≤
0.2V.
Output Disable.
The data outputs are high im-
pedance when the Output Enable (GS) is at V
IH
with Write Enable (WS) at V
IH
.
E2S
≤
0.2V
or
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