參數(shù)資料
型號: M36L0T7050
廠商: 意法半導(dǎo)體
英文描述: 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package
中文描述: 128兆位(多銀行,多層次,突發(fā))閃存32兆位(200萬× 16)移動存儲芯片,1.8V電源多芯片封裝
文件頁數(shù): 9/18頁
文件大?。?/td> 406K
代理商: M36L0T7050
9/18
M36L0R7050T0, M36L0R7050B0
Table 2. Main Operating Modes
Note: 1. X = Don't care.
2. L
F
can be tied to V
IH
if the valid address has been previously latched.
3. Depends on G
F
.
4. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R7000T0 datasheet for details.
Operation
E
F
G
F
W
F
L
F
RP
F
WAIT
F(4)
E1
P
E2
P
G
P
W
P
LB
P
UB
P
DQ15-DQ0
Flash Read
V
IL
V
IL
V
IH
V
IL(2
)
V
IH
PSRAM must be disabled
Flash Data Out
Flash Write
V
IL
V
IH
V
IL
V
IL(2
)
V
IH
Flash Data In
Flash Address
Latch
V
IL
X
V
IH
V
IL
V
IH
Flash Data Out
or Hi-Z
(3)
Flash Output
Disable
V
IL
V
IH
V
IH
X
V
IH
Any PSRAM mode is allowed
Hi-Z
Flash Standby
V
IH
X
X
X
V
IH
Hi-Z
Hi-Z
Flash Reset
X
X
X
X
V
IL
Hi-Z
Hi-Z
PSRAM Read
Flash Memory must be disabled
V
IL
V
IH
V
IL
V
IH
V
IH
V
IL
Upper Byte
data out
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
Lower Byte
data out
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
Word Read
PSRAM Write
V
IL
V
IH
V
IH
V
IL
V
IH
V
IL
Upper Byte
data in
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
Lower Byte
data in
V
IL
V
IH
V
IH
V
IL
V
IL
V
IL
Word Write
Output Disable
Any Flash mode is allowed
V
IL
V
IH
V
IL
V
IH
V
IH
V
IH
Hi-Z
V
IL
V
IH
V
IH
V
IL
V
IH
V
IH
PSRAM
Standby
(Deselected)
V
IH
V
IH
X
X
X
X
Hi-Z
PSRAM Power-
Down
X
V
IL
X
X
X
X
Hi-Z
相關(guān)PDF資料
PDF描述
M36L0R7050B0ZAQF CAP 0.1UF 50V 10% X7R DIP-2 BULK P-MIL-C-39014
M36L0R7050B0ZAQT CAP 2.2PF 200V 0.5PF C0H DIP-2 BULK S-MIL-C-39014
M36L0R7050B0ZAQE ER 23C 16 12 8 4 SKT RECP WALL
M36L0R7050T0ZAQE AB 6C 2#0 4#4 SKT RECP
M36L0R7050T0ZAQT 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package
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