參數(shù)資料
型號: M37161MF-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
封裝: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù): 13/129頁
文件大?。?/td> 1092K
代理商: M37161MF-XXXSP
Rev.1.00
2003.11.25
page 11 of 128
M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
8. FUNCTION BLOCK DESCRIPTION
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Availability of 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
8.1.1 CPU Mode Register
The CPU mode register includes a stack page selection bit and inter-
nal system clock selection bit. The CPU mode register is allocated at
address 00FB16.
Fig. 8.1.1 CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
After reset RW
CPU Mode Register
0, 1
2
3, 4
0
1
Name
Functions
Processor mode bits
(CM0, CM1)
0 0: Single-chip mode
0 1:
1 0:
Not available
1 1:
Fix these bits to “1.”
1
Stack page selection
bit (CM2) (See note1)
1
b1 b0
0: 0 page
1: 1 page
1
0
5
1
6
0
Main Clock (XIN-XOUT)
stop bit (CM6)
CPU mode register (CM) [Address 00FB16]
R W
RW
R W
RW
XCOUT drivability
selection bit (CM5)
0: LOW drive
1: HIGH drive
0: Oscillating
1: Stopped
7
0
Internal system clock
selection bit
(CM7)
RW
0: XIN-XOUT selected
(high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Note 1: This bit is set to “1” after the reset release.
B
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