Rev.1.00
2003.11.25
page 120 of 128
M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
W
R
Interrupt Request Register 1
0
B
Name
Functions
Afrer reset
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt request
bit (TM1R)
1
Timer 2 interrupt request
bit (TM2R)
2
Timer 3 interrupt request
bit (TM3R)
3
Timer 4 interrupt request
bit (TM4R)
4
OSD interrupt
request bit (OSDR)
5
VSYNC interrupt request
bit (VSCR)
6
INT3 external interrupt
request bit (IN3R)
7
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
: “0” can be set by software, but “1” cannot be set.
—
R
R
R
R
R
R
R
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
b7 b6 b5 b4 b3 b2 b1 b0
After reset RW
CPU Mode Register
0, 1
2
3, 4
0
1
Name
Functions
Processor mode bits
(CM0, CM1)
0 0: Single-chip mode
0 1:
1 0:
Not available
1 1:
Fix these bits to “1.”
1
Stack page selection
bit (CM2) (See note1)
1
b1 b0
0: 0 page
1: 1 page
1
0
5
1
6
0
Main Clock (XIN-XOUT)
stop bit (CM6)
CPU mode register (CM) [Address 00FB16]
R W
RW
R W
RW
XCOUT drivability
selection bit (CM5)
0: LOW drive
1: HIGH drive
0: Oscillating
1: Stopped
7
0
Internal system clock
selection bit
(CM7)
RW
0: XIN-XOUT selected
(high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Note 1: This bit is set to “1” after the reset release.
B
Address 00FB16
Address 00FC16