參數(shù)資料
型號: M37161MF-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
封裝: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù): 83/129頁
文件大?。?/td> 1092K
代理商: M37161MF-XXXSP
Rev.1.00
2003.11.25
page 57 of 128
M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
Fig. 8.10.8 Vertical Position Register i (i = 1 and 2)
The vertical display start position for each block can be set in 512
steps (where each step is 1TH (TH: HSYNC cycle)) as values “0016” to
“FF16” in vertical position register i (i = 1 and 2) (addresses 00D416
and 00D516) and values “0” or “1” in bit 6 of block control register i (i
= 1 and 2) (addresses 00D216 and 00D316). The vertical position
register is shown in Figure 8.10.8.
The vertical display start position of both blocks can be switched in
each step to 1TH or 2TH by setting values “0” or “1” in bit 1 of OSD
control register 2 (address 00DB16).
b7 b6 b5 b4 b3 b2 b1 b0
0
to
7
R W
Vertical Position Register i
Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516]
B
Name
Functions
After reset
RW
Inderterminate
Vertical display start
position control bits
(VPi0 to VPi7)
(See notes)
Vertical display start position =
TH (BCi6 16
2 + n)
(n: setting value, TH: HSYNC cycle,
BCi6: bit 6 of block control register i)
Notes 1: Set values except “0016” to VPi when BCi6 is “0.”
2: When OS21 of OSD control register 2 = “0”, TH = 1HSYNC,
and OS21 of OSD control register 2 = “1”, TH = 2HSYNC.
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