參數(shù)資料
型號： M37512F8H-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù)： 11/89頁
文件大?。?/td> 877K
代理商： M37512F8H-XXXHP
Feb 18, 2005
page 17 of 85
REJ03B0122-0101
7512 Group
Fig. 12 Interrupt control
Fig. 13 Structure of interrupt-related registers
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
Interrupt control register 1
0 : No interrupt request issued
1 : Interrupt request issued
(ICON1 : address 003E16)
Interrupt request register 2
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 reception interrupt request bit
Serial I/O1 transmit / Over current detect interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
AD converter /current integrate interrupt request bit
Not used (returns “0” when read)
(IREQ2 : address 003D16)
Interrupt control register 2
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit / Over current detect interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
AD converter / current integrate interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16)
Interrupt request register 1
INT0 interrupt request bit
SCL/SDA interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
INT3 / Serial I/O2 interrupt request bit
I2C interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
(IREQ1 : address 003C16)
0 : No interrupt request issued
1 : Interrupt request issued
INT0 interrupt enable bit
SCL/SDA interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
INT3 / Serial I/O2 interrupt enable bit
I2C interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
INT0 active edge selection bit
0 : Falling edge active
1 : Rising edge active
INT1 active edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
Serial I/O2 / INT3 interrupt source bit
0 : INT3 interrupt selected
1 : Serial I/O2 interrupt selected
Current integrate/A/D converter interrupt source bit
0 : AD converter interrupt selected
1 : Current integrate interrupt selected
Over current detect / Serial I/O1 transmit interrupt source bit
0 : Serial I/O1 transmit interrupt selected
1 : Over current detect interrupt selected
Not used (returns “0” when read)
Interrupt edge selection register 1
(INTEDGE1 : address 003A16)
INT2 falling edge active bit
0 : No operation
1 : Falling edge active
INT2 rising edge active bit
0 : No operation
1 : Rising edge active
INT3 falling edge active bit
0 : No operation
1 : Falling edge active
INT3 rising edge active bit
0 : No operation
1 : Rising edge active
Not used (returns “0” when read)
b7
b0 Interrupt edge selection register 2
(INTEDGE2 : address 0FF516)
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