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參數(shù)資料
| 型號： | M37641M8-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 69/136頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | M37641M8-XXXFP |
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38
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 31 DMACx (x = 0, 1) block diagram
DMAC
The 7641 group is equipped with 2 channels of DMAC (direct
memory access controller) which enable high speed data transfer
from a memory to a memory without use of the CPU.
The DMAC initiates the data transfer with an interrupt factor speci-
fied by the DMAC channel x (x = 0, 1) hardware transfer request
source bit (DxCEN), or with a software trigger.
The DxTMS [DMA Channel x (x = 0, 1) Transfer Mode Selection
Bit] selects one of two transfer modes; cycle steal mode or burst
transfer mode. In the cycle steal mode, the DMAC transfers one
byte of data for each request. In the burst transfer mode, the
DMAC transfers the number of bytes data specified by the transfer
count register for each request. The count register is a 16-bit
counter; the maximum number of data is 65,536 bytes per one re-
quest.
Figure 31 shows the DMA control block diagram and Figure 32
shows the structure of DMAC related registers.
[DMAC Index and Status Register] DMAIS
The DMAC Index and Status Register consists of various control
bits for the DMAC and its status flags.
The DMA Channel Index Bit (DCI) selects which channel ( 0 or 1)
will be accessed, since the mode registers, source registers, des-
tination registers and transfer count register of both DMAC
channels share the same SFR addresses, respectively.
[DMAC Channel x (x = 0, 1) Mode Registers 1, 2] DMAxM1,
DMAxM2
The 16 bits of DMAC Channel x Mode Registers 1 and 2 control
each operation of DMAC channels 0 and 1.
When the DMAC Channel x (x = 0, 1) Write Bit (DxDWC) is “0”,
data is simultaneously written into each latch and register of the
Source Registers, Destination Register, and Transfer Count Reg-
isters. When this bit is “1”, data is written only into their latches.
When data is read from each register, it must be read from the
higher bytes first, then the lower bytes. When writing data, write to
the lower bytes first, then the higher bytes.
Interrupt:
UART1 receive, UART1 transmit,
Serial I/O, INT0, Timer Y, CNTR1
Signal:
OBE0, IBF0 (data),
EP (endpoint) 1 receive/transmit
EP (endpoint) 2 receive/transmit
EP (endpoint) 3 receive/transmit
EP1OUT FIFO data existing
Interrupt:
UART2 receive, UART2 transmit,
INT1, Timer 1, Timer X, CNTR0
Signal:
OBE1, IBF1 (data),
EP (endpoint) 1 receive/transmit
EP (endpoint) 2 receive/transmit
EP (endpoint) 4 receive/transmit
EP1OUT FIFO data existing
Case of DMAC
channel 0
Case of DMAC
channel 1
DMAC channel X
Channel X timing
generator
Channel X transfer
source register
Channel X transfer
destination register
Channel X transfer count register
Interrupt
generator
DMACx
interrupt request
Address bus
DxCEN
DxCRR
DxUMIE
DxSWT
DxHRS3
DxHRS2
DxHRS1
DxHRS0
DxSRCE
DxSRID
DxRLD
DRLDD
DxDRCE
DxDRID
DxRLD
DRLDD
Interrupt disable flag (I flag)
Temporary register
Index status register
DxUF
DxDAUE
Mode 1
register
DxTMSDTSC
Mode 2
register
Channel X transfer
source latch
Channel X transfer
destination latch
Channel X transfer count latch
DxDWC
Data bus
DxUF
DxSFI
15
0
150
15
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M37641M8-XXXHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M376420RS | 制造商:OKI 功能描述:3764-20 NOTES |
| M3764-20RS | 制造商:OKI 功能描述:3764-20 NOTES 制造商: 功能描述:Dynamic RAM, Page Mode, 64K x 1, 16 Pin, Plastic, DIP 制造商:OK International 功能描述:Dynamic RAM, Page Mode, 64K x 1, 16 Pin, Plastic, DIP |
| M3-7643A-S | 制造商:Harris Corporation 功能描述: |
| M37643F8E8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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