參數(shù)資料
型號: M37641M8-XXXFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 89/136頁
文件大?。?/td> 1672K
代理商: M37641M8-XXXFP
56
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[USB Endpoint x (x = 0 to 4) IN Max. Packet Size Register]
IN_MAXP
This register specifies the maximum packet size (MAXP) of an
endpoint x IN packet. The value set for endpoint 1 is the number
of transmitted bytes divided by 8, and the value set for endpoints
0, 2, 3, and 4 is the actual number of transmitted bytes. The CPU
can change these values using the SET_DESCRIPTOR com-
mand.
The initial value for endpoints 0, 2, 3 and 4 is 8, and the initial
value for endpoint 1 is 1.
[USB Endpoint x (x = 0 to 4) OUT Max. Packet Size Register]
OUT_MAXP
This register specifies the maximum packet size (MAXP) of an
Endpoint x OUT packet. The value set for endpoint 1 is the num-
ber of received bytes divided by 8, and the value set for endpoints
0, 2, 3, and 4 is the actual number of received bytes. The CPU
can change these values using the SET_DESCRIPTOR com-
mand.
The initial value for endpoints 0, 2, 3, and 4 is 8, and the initial
value for endpoint 1 is 1. When using the endpoint 0, both USB
endpoint x IN max. packet size register (IN _MAXP) and USB end-
point x OUT max. packet size register (OUT_MAXP) are set to the
same value. Changing one register’s value effectively changes the
value of the other register as well.
The maximum packet size (MAXP) of endpoint x IN is contained.
MAXP = n for endpoints 0, 2, 3, 4
MAXP = n 8 for endpoint 1
“n” is a written value into this register.
USB endpoint x IN max. packet size register (address 005B16)
IN_MAXP
b0
b7
The maximum packet size (MAXP) of endpoint x OUT is contained.
MAXP = n for endpoints 0, 2, 3, 4
MAXP = n 8 for endpoint 1
“n” is a written value into this register.
USB endpoint x OUT max. packet size register (address 005C16)
OUT_MAXP
b0
b7
Fig. 49 Structure of USB endpoint x IN max. packet size register
Fig. 50 Structure of USB endpoint x OUT max. packet size register
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