參數(shù)資料
型號: M37754M8C-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 103/115頁
文件大小: 1571K
代理商: M37754M8C-XXXGP
87
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
READY, HOLD TIMING
Timing requirements (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit = “0”, unless
otherwise noted)
The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted.
tsu(RDY-
φ1)
tsu(HOLD-
φ1)
th(
φ1-RDY)
th(
φ1-HOLD)
Symbol
RDY input setup time
HOLD input setup time
RDY input hold time
HOLD input hold time
Parameter
Limits
Min.
42
0
Max.
ns
Unit
: f(XIN) = 20 MHz when the clock source select bit = “1”.
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit =
“0”, unless otherwise noted)
td(
φ1-HLDA)
tpxz(HLDA-RDZ)
tpxz(HLDA-WRZ)
tpxz(HLDA-BHEZ)
tpxz(HLDA-AZ)
tpxz(HLDA-DLZ/DHZ)
tpzx(HLDA-RDZ)
tpzx(HLDA-WRZ)
tpzx(HLDA-BHEZ)
tpzx(HLDA-AZ)
tpzx(HLDA-DLZ/DHZ)
Symbol
HLDA output delay time
Floating release delay time (at hold state)
Parameter
Min.
Limits
Max.
50
ns
Unit
0
: f(XIN) = 20 MHz when the clock source select bit = “1”.
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