參數(shù)資料
型號(hào): M37754M8C-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 107/115頁(yè)
文件大小: 1571K
代理商: M37754M8C-XXXGP
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90
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz when the clock source select bit = “0”, unless
otherwise noted)
V The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted.
Memory expansion and Microprocessor mode : Low-speed running
ns
Unit
tc
tw(H)
tw(L)
tr
tf
tsu(DH-RD)
tsu(DL-RD)
tsu(PiD–RD)
th(RD-DH)
th(RD-DL)
th(RD–PiD)
tsu(A–DL/DH)
tsu(CS–DL/DH)
tsu(LA–DL)
Symbol
External clock input cycle time (Note 1)
External clock input high-level pulse width (Note 2)
External clock input low-level pulse width (Note 2)
External clock rise time
External clock fall time
High-order data input setup time (BYTE = “L”)
Low-order data input setup time
Port Pi input setup time (i = 4—9, 11)
High-order data input hold time (BYTE = “L”)
Low-order data input hold time
Port Pi input hold time (i = 4—9, 11)
Data setup time with address stabilized (Note 3)
Data setup time with chip select stabilized (Note 3)
Data setup time with address stabilized (Note 3)
Parameter
Min.
40
tc/2 – 8
30
60
0
Limits
Max.
8
60 (2-
φ access)
140 (3-
φ access)
220 (4-
φ access)
60 (2-
φ access)
140 (3-
φ access)
220 (4-
φ access)
55 (2-
φ access)
135 (3-
φ access)
215 (4-
φ access)
: f(XIN) = 12.5 MHz when the clock source selet bit = “1”
Notes 1: When the clock source select bit = “1”, tc’s minimum limit is 80 ns.
2: When the clock source select bit = “1”, set tw(H)/tc and tw(L)/tc ratios to 45 to 55 %.
3: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the page after
the next page.
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