參數(shù)資料
型號: M37905M4C-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 64/102頁
文件大小: 881K
代理商: M37905M4C-XXXFP
64
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table 8. Selection methods of CTS/RTS function
CTSi/RTSi
separate select bit
0
1
Functions
CTS0
RTS0
P10
Pin P11/CTS0/CLK0
P11 or CLK0
CTS0 (Notes 1, 2)
P11 or CLK0
Pin P14/CTS1/RTS1 Pin P15/CTS1/CLK1
CTS/RTS
function select bit
CTS/RTS
enable bit
0
1
0
1
Pin P10/CTS0/RTS0
CTS1
RTS1
P14
P15 or CLK1
CTS1 (Notes 1 and 2)
P15 or CLK1
Pin P80/CTS2/RTS2 Pin P81/CTS2/CLK2
CTS2
RTS2
P80
P81 or CLK2
Notes 1: When using the CTS function, be sure to clear the corresponding bit of the port P1 and port P8 direction registers to “0”.
2: When CTSi and RTSi has been separated, the CLKi pin cannot be used. Therefore, in the clock synchronous serial communication, CTSi and RTSi
cannot be separated. Also, when CTSi and RTSi are separated in UART mode, be sure to select an internal clock.
: It may be “0” or “1”.
CTS2 (Notes 1, 2)
Fig. 72 Bit configuration of serial I/O pin control register
Receive
Receive is enabled when bit 2 (REi flag) of UARTi transmit/receive
control register 1 is set to “1.” As shown in Figure 71, the frequency
divider circuit (1/16) at the receiving side begin to work when a start
bit arrives and the data is received.
If RTSi output is selected by setting bit 2 of UARTi transmit/receive
control register 0 to “1”, the RTSi output is “H” when the REi flag is
“0”. When the REi flag changes to “1”, the RTSi output goes “L” to
inform the receiver that reception has become enabled. When the
receive operation starts, the RTSi output automatically becomes “H”.
The entire transmission data bits are received when the start bit
passes the final bit of the receive block shown in Figure 62. At this
point, the contents of the receive register is transferred to the receive
buffer register and bit 3 (Rli flag) of UARTi transmit/receive control
register 1 is set to “1.” In other words, the RIi flag indicates that the
receive buffer register contains data when it is set to “1.” At this time,
when the low-order byte of the UARTk receive buffer register is read
out, RTSi output goes back to “L” to indicate that the register is ready
to receive the next data.
Bit 4 (OERi flag) of UARTi transmit/receive control register 1 is set to
“1” when the next data is transferred from the receive register to the
receive buffer register while the RIi flag is “1”, in other words, when
an overrun error occurs. If the OERi flag is “1”, it indicates that the
next data has been transferred to the receive buffer register before
the contents of the receive buffer register has been read.
Bit 5 (FERi flag) is set to “1” when the number of stop bits is less than
required (framing error).
Bit 6 (PERi flag) is set to “1” when a parity error occurs.
Bit 7 (SUMi flag) is set to “1” when either the OERi flag, FERi flag, or
the PERi flag is set to “1.” Therefore, the SUMi flag can be used to
determine whether there is an error.
The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag is
performed while transferring the contents of the receive register to
the receive buffer register.
CTS0/RTS0 separate select bit
0 : CTS0/RTS0 are used together.
1 : CTS0/RTS0 are separated.
CTS1/RTS1 separate select bit
0 : CTS1/RTS1 are used together.
1 : CTS1/RTS1 are separated.
TxD0/P13 switch bit
0 : Functions as TxD0.
1 : Functions as P13.
TxD1/P17 switch bit
0 : Functions as TxD1.
1 : Functions as P17.
CTS2/RTS2 separate select bit
0 : CTS2/RTS2 are used together.
1 : CTS2/RTS2 are separated.
TxD2/P83 switch bit
0 : Functions as TxD2.
1 : Functions as P83.
76543210
Serial I/O pin control register
Address
AC16
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