參數(shù)資料
型號： M38039GCH-XXXWG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.65 PITCH, FLGA-64
文件頁數(shù)： 100/103頁
文件大小： 1412K
代理商： M38039GCH-XXXWG
REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 96 of 100
3803 Group (Spec.H QzROM version)
NOTES:
1. When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
Table 20
Switching characteristics (1)
(VCC = 2.0 to 5.5 V, VSS = 0V, Ta =
20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test
conditions
Limits
Unit
Min.
Typ.
Max.
tWH(SCLK1)
tWH(SCLK3)
Serial I/O1, serial I/O3
clock output “H” pulse
width
4.5
≤ VCC ≤ 5.5 V
tC(SCLK1)/2-30, tC(SCLK3)/2-30
ns
4.0
≤ VCC < 4.5 V
tC(SCLK1)/2-35, tC(SCLK3)/2-35
2.7
≤ VCC < 4.0 V
tC(SCLK1)/2-40, tC(SCLK3)/2-40
2.2
≤ VCC < 2.7 V
tC(SCLK1)/2-45, tC(SCLK3)/2-45
2.0
≤ VCC < 2.2 V
tC(SCLK1)/2-50, tC(SCLK3)/2-50
tWL(SCLK1)
tWL(SCLK3)
Serial I/O1, serial I/O3
clock output “L” pulse
width
4.5
≤ VCC ≤ 5.5 V
tC(SCLK1)/2-30, tC(SCLK3)/2-30
ns
4.0
≤ VCC < 4.5 V
tC(SCLK1)/2-35, tC(SCLK3)/2-35
2.7
≤ VCC < 4.0 V
tC(SCLK1)/2-40, tC(SCLK3)/2-40
2.2
≤ VCC < 2.7 V
tC(SCLK1)/2-45, tC(SCLK3)/2-45
2.0
≤ VCC < 2.2 V
tC(SCLK1)/2-50, tC(SCLK3)/2-50
td(SCLK1-TxD1)
td(SCLK3-TxD3)
Serial I/O1, serial I/O3
output delay time(1)
4.5
≤ VCC ≤ 5.5 V
140
ns
4.0
≤ VCC < 4.5 V
200
2.7
≤ VCC < 4.0 V
350
2.2
≤ VCC < 2.7 V
400
2.0
≤ VCC < 2.2 V
420
tV(SCLK1-TxD1)
tV(SCLK3-TxD3)
Serial I/O1, serial I/O3
output valid time(1)
4.5
≤ VCC ≤ 5.5 V
30
ns
4.0
≤ VCC < 4.5 V
30
2.7
≤ VCC < 4.0 V
30
2.2
≤ VCC < 2.7 V
30
2.0
≤ VCC < 2.2 V
30
tr(SCLK1)
tr(SCLK3)
Serial I/O1, serial I/O3
rise time of clock
output
4.5
≤ VCC ≤ 5.5 V
30
ns
4.0
≤ VCC < 4.5 V
35
2.7
≤ VCC < 4.0 V
40
2.2
≤ VCC < 2.7 V
45
2.0
≤ VCC < 2.2 V
50
tf(SCLK1)
tf(SCLK3)
Serial I/O1, serial I/O3
fall time of clock output
4.5
≤ VCC ≤ 5.5 V
30
ns
4.0
≤ VCC < 4.5 V
35
2.7
≤ VCC < 4.0 V
40
2.2
≤ VCC < 2.7 V
45
2.0
≤ VCC < 2.2 V
50
tWH(SCLK2)
Serial I/O2
clock output “H” pulse
width
4.5
≤ VCC ≤ 5.5 V
tC(SCLK2)/2-160
ns
4.0
≤ VCC < 4.5 V
tC(SCLK2)/2-200
2.7
≤ VCC < 4.0 V
tC(SCLK2)/2-240
2.2
≤ VCC < 2.7 V
tC(SCLK2)/2-260
2.0
≤ VCC < 2.2 V
tC(SCLK2)/2-280
tWL(SCLK2)
Serial I/O2
clock output “L” pulse
width
4.5
≤ VCC ≤ 5.5 V
tC(SCLK2)/2-160
ns
4.0
≤ VCC < 4.5 V
tC(SCLK2)/2-200
2.7
≤ VCC < 4.0 V
tC(SCLK2)/2-240
2.2
≤ VCC < 2.7 V
tC(SCLK2)/2-260
2.0
≤ VCC < 2.2 V
tC(SCLK2)/2-280
td(SCLK2-SOUT2) Serial I/O2
output delay time
4.5
≤ VCC ≤ 5.5 V
200
ns
4.0
≤ VCC < 4.5 V
250
2.7
≤ VCC < 4.0 V
300
2.2
≤ VCC < 2.7 V
350
2.0
≤ VCC < 2.2 V
400
tV(SCLK2-SOUT2)
Serial I/O2
output valid time
4.5
≤ VCC ≤ 5.5 V
0
ns
4.0
≤ VCC < 4.5 V
0
2.7
≤ VCC < 4.0 V
0
2.2
≤ VCC < 2.7 V
0
2.0
≤ VCC < 2.2 V
0
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