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參數(shù)資料
| 型號： | M38039GCH-XXXWG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.65 PITCH, FLGA-64 |
| 文件頁數(shù)： | 81/103頁 |
| 文件大小： | 1412K |
| 代理商： | M38039GCH-XXXWG |
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REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 79 of 100
3803 Group (Spec.H QzROM version)
6. Serial Interface
In clock synchronous serial I/O, if the receive side is using an
external clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O1 continues to output the final bit from the TXD1 pin
after transmission is completed. SOUT2 pin for serial I/O2 goes to
high impedance after transfer is completed.
When in serial I/Os 1 and 3 (clock-synchronous mode) or in
serial I/O2, an external clock is used as synchronous clock, write
transmission data to the transmit buffer register or serial I/O2
register, during transfer clock is “H”.
7. A/D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) in the middle/high-speed mode
is at least on 500 kHz during an A/D conversion.
Do not execute the STP instruction during an A/D conversion.
8. D/A Converter
The accuracy of the D/A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of VCC
≥ 4.0
V is recommended. When a D/A converter is not used, set all
values of DAi conversion registers (i=1, 2) to “0016”.
9. Instruction Execution Time
The instruction execution time is obtained by multiplying the
period of the internal clock
φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock
φ is double of the XIN period in
high-speed mode.
10.Reserved Area, Reserved Bit
Do not write any data to the reserved area in the SFR area and the
special page. (Do not change the contents after reset.)
11.CPU Mode Register
Be sure to fix bit 3 of the CPU mode register (address 003B16) to
“1”.
COUNTERMEASURES AGAINST NOISE
(1) Shortest wiring length
1. Wiring for RESET pin
Make the length of wiring which is connected to the RESET
pin as short as possible. Especially, connect a capacitor across
the RESET pin and the VSS pin with the shortest possible
wiring (within 20 mm).
Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is
completely initialized. This may cause a program runaway.
Fig. 76 Wiring for the RESET pin
2. Wiring for clock input/output pins
Make the length of wiring which is connected to clock I/O
pins as short as possible.
Make the length of wiring (within 20 mm) across the
grounding lead of a capacitor which is connected to an
oscillator and the VSS pin of a microcomputer as short as
possible.
Separate the VSS pattern only for oscillation from other VSS
patterns.
Reason
If noise enters clock I/O pins, clock waveforms may be
deformed.
This may cause a program failure or program runaway. Also, if a
potential difference is caused by the noise between the VSS level
of a microcomputer and the VSS level of an oscillator, the correct
clock will not be input in the microcomputer.
Fig. 77 Wiring for clock I/O pins
RESET
Reset
circuit
Noise
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Noise
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
O.K.
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