參數(shù)資料
型號(hào)： M38039GCH-XXXWG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.65 PITCH, FLGA-64
文件頁數(shù)： 45/103頁
文件大?。?/td> 1412K
代理商： M38039GCH-XXXWG
REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 46 of 100
3803 Group (Spec.H QzROM version)
SERIAL INTERFACE
Serial I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O. A dedicated timer is also
provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control
register (bit 6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Fig 36. Block diagram of clock synchronous serial I/O1
Fig 37. Operation of clock synchronous serial I/O1
Serial I/O1 control register
Receive buffer register 1
Receive shift register 1
Clock control circuit
1/4
Baud rate generator 1
f(XIN)
1/4
Clock control circuit
Falling-edge detector
Transmit buffer register 1
Transmit shift register 1
Serial I/O1 status register
F/F
Address 001816
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Shift clock
Serial I/O1 synchronous clock selection bit
Frequency division ratio 1/(n+1)
Address 001C16
BRG count source selection bit
Address 001816
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Address 001A16
Data bus
P46/SCLK1
P44/RXD1
P45/TXD1
(f(XCIN) in low-speed mode)
P47/SRDY1
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD1
Serial input RXD1
Write pulse to receive/transmit
buffer register 1 (address 001816)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register 1 when TSC=0, the transmit clock is generated continuously and serial data is output
continuously from the TXD1 pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Receive enable signal SRDY1
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