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參數(shù)資料
| 型號(hào)： | M38039GCH-XXXWG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.65 PITCH, FLGA-64 |
| 文件頁(yè)數(shù)： | 65/103頁(yè) |
| 文件大?。?/td> | 1412K |
| 代理商： | M38039GCH-XXXWG |
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REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 64 of 100
3803 Group (Spec.H QzROM version)
D/A CONVERTER
The 3803 group (Spec.H QzROM version) has two internal D/A
converters (DA1 and DA2) with 8-bit resolution.
The D/A conversion is performed by setting the value in each
DAi conversion register (i = 1 or 2). The result of D/A
conversion is output from the DA1 or DA2 pin by setting the DAi
output enable bit (i = 1 or 2) to “1”.
When using the D/A converter, the corresponding port direction
register bit (P30/DA1 or P31/DA2) must be set to “0” (input
status).
The output analog voltage V is determined by the value n
(decimal notation) in the DAi conversion register (i = 1 or 2) as
follows:
V = VREF× n/256 (n = 0 to 255)
Where VREF is the reference voltage.
At reset, the DAi conversion register (i = 1 or 2) is cleared to
“0016”, and the DAi output enable bit (i = 1 or 2) is cleared to
“0”, an d the P30 /DA 1 and P 31 /DA 2 pi ns b eco me hi gh
impedance.
The DA output does not have buffers. Accordingly, connect an
external buffer when driving a low-impedance load.
Fig 57. Block diagram of D/A converter
Fig 58. Equivalent connection circuit of D/A converter (DA1)
DA1 conversion register (8)
DA1 output enable bit
P30/DA1
Da
ta
b
u
s
R-2R resistor ladder
DA2 conversion register (8)
DA2 output enable bit
P31/DA2
R-2R resistor ladder
DA1 output enable bit
AVSS
VREF
R
2R
R
2R
LSB
“1”
“0”
MSB
DA1 conversion register
P30/DA1
“0”
“1”
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