參數(shù)資料
型號(hào)： M38259EFFS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CQCC100
封裝： CERAMIC, LCC-100
文件頁(yè)數(shù)： 37/73頁(yè)
文件大?。?/td> 1323K
代理商： M38259EFFS
Rev.2.02
Jun 19, 2007
page 40 of 73
REJ03B0146-0202
3823 Group
LCD DRIVE CONTROL CIRCUIT
The 3823 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
●LCD display RAM
●Segment output enable register
●LCD mode register
●Selector
●Timing controller
●Common driver
●Segment driver
●Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
Up to 128 pixels can be controlled for LCD display. When the LCD
Fig. 36 Structure of segment output enable register and LCD mode register
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
Table 10 Maximum number of display pixels at each duty ratio
Duty ratio
Maximum number of display pixel
64 dots
or 8 segment LCD 8 digits
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
2
3
4
LCD mode register
(LM : address 003916)
Segment output enable register
(SEG : address 003816)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 (use COM0, COM1)
1 0 : 3 (use COM0–COM2)
1 1 : 4 (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(SUB)/32
1 : f(XIN)/8192 (or f(SUB)/8192 in low-speed
mode)
Note: LCDCK is a clock for a LCD timing controller.
f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation
frequency of XCIN or the on-chip oscillator.
Internal clock φ is f(SUB)/2 in the low-speed mode.
Segment output enable bit 0
0 : Input port P34–P37
1 : Segment output SEG12–SEG15
Segment output enable bit 1
0 : I/O port P00,P01
1 : Segment output SEG16, SEG17
Segment output enable bit 2
0 : I/O port P02–P07
1 : Segment output SEG18–SEG23
Segment output enable bit 3
0 : I/O port P10,P11
1 : Segment output SEG24, SEG25
Segment output enable bit 4
0 : I/O port P12
1 : Segment output SEG26
Segment output enable bit 5
0 : I/O port P13–P17
1 : Segment output SEG27–SEG31
Not used (returns “0” when read)
(Do not write
“1” to this bit.)
b7b0
b7
b0
相關(guān)PDF資料
PDF描述
M38254M6DXXXFP 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP100
M38258MCDXXXFP 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP100
M38257M8-XXXFP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP100
M38254M6-XXXGP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP100
M38257E8GP 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M3826 功能描述:電纜固定件和配件 LTRSCG 1000 BLACK RoHS:否 制造商:Heyco 類(lèi)型:Cable Grips, Liquid Tight 材料:Nylon 顏色:Black 安裝方法:Cable 最大光束直徑:11.4 mm 抗拉強(qiáng)度:
M3826 BK001 制造商:Alpha Wire Company 功能描述:CBL 2COND 16AWG BLK 1000'
M3826 BK002 制造商:Alpha Wire Company 功能描述:CBL 2COND 16AWG BLK 500'
M3826 BK005 制造商:Alpha Wire Company 功能描述:CBL 2COND 16AWG BLK 100'
M3826 BK199 制造商:Alpha Wire Company 功能描述:CBL 2COND 16AWG BLK 3000=3000'
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*