參數(shù)資料
型號(hào)： M3826AMFA-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 19/93頁
文件大?。?/td> 996K
代理商： M3826AMFA-XXXFP
Rev.2.00
May. 24, 2006
page 26 of 90
REJ03B0028-0200
3826 Group (A version)
TIMERS
The 3826 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Fig. 22 Timer block diagram
“1”
P55/CNTR1
“0”
“10”
“00”,“01”,“11”
P54/CNTR0
Q
T
S
“0”
“1”
“0”
Q D
“0”
Q D
“1”
“0”
“1”
“10”
Q
T
S
“0”
“1”
“0”
“1”
P43/
φ/TOUT
XCIN
“0”
“1”
CNTR0 active
edge switch bit
Timer 1 count source
selection bit
Real time port
control bit “0”
f(XIN)/16
(f(XCIN)/16
when
φ = XCIN/2)
CNTR1 active
edge switch bit
Timer Y stop
control bit
Falling edge detection
Period
measurement mode
Timer Y
interrupt
request
Pulse width HL continuously
measurement mode
Rising edge detection
Timer Y
operating
mode bits
Timer X
interrupt
request
Timer X mode register
write signal
P43 direction
register
Pulse output mode
P54 latch
Timer X stop
control bit
Timer X write
control bit
Latch
Timer X operat-
ing mode bits
“00”,“01”,“11”
Pulse width
measurement
mode
CNTR0 active
edge switch bit
Pulse output mode
P54 direction register
TOUT output
active edge
switch bit “0”
Timer 2 write
control bit
Timer 3 count
source selection bit
Timer 2
interrupt
request
Timer 3
interrupt
request
Timer 2 count source
selection bit
Timer 1
interrupt
request
Data bus
Real time port
control bit “1”
Real time port
control bit “1”
Timer 3 latch (8)
Timer 3 register (8)
Timer 1 latch (8)
Timer 1 register (8)
Timer 2 latch (8)
Timer 2 register (8)
Timer X low-order register (8)
Timer X (low) latch (8)
Timer X (high) latch (8)
Timer Y (low) latch (8)
Timer Y (high) latch (8)
Latch
P43 latch
f(XIN)/16
(f(XCIN)/16 when
φ = XCIN/2)
f(XIN)/16
(f(XCIN)/16 when
φ = XCIN/2)
f(XIN)/16
(f(XCIN)/16 when
φ = XCIN/2)
f(XIN)/16
(f(XCIN)/16 when
φ = XCIN/2)
P52/RTP0
P53/RTP1
RTP0 data for
real time port
RTP1 data for
real time port
P52 direction register
P52 latch
P53 direction register
P53 latch
φ
Timer X high-order register (8)
Timer Y low-order register (8)
Timer Y high-order register (8)
Q
TOUT/
φ
output
selection bit
TOUT/
φ
output
enable bit
TOUT/
φ output
enable bit
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