參數(shù)資料
型號(hào)： M3826AMFA-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁(yè)數(shù)： 87/93頁(yè)
文件大?。?/td> 996K
代理商： M3826AMFA-XXXFP
Rev.2.00
May. 24, 2006
page 88 of 90
REJ03B0028-0200
3826 Group (A version)
3.3.12 Notes on watchdog timer
(1) The watchdog timer is operating during the wait mode. Write data to the watchdog timer control
register to prevent timer underflow.
(2) The watchdog timer stops during the stop mode. However, the watchdog timer is running during the
clock stabilization period and the watchdog timer control register must be written just before executing
the STP instruction.
(3) The count source of the watchdog timer is affected by the system clock
φ selected by the system
clock selection bit (bit 7 of CPU mode register (address 3B16)).
3.3.13 Notes on reset circuit
(1)
Reset input voltage control
Make sure that the reset input voltage is less than 0.2 Vcc for Vcc(min).
(2)
Countermeasures for reset signal slow rising
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across
the RESET pin and the Vss pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following:
Make the length of the wiring which is connected to a capacitor as short as possible.
Be sure to verify the operation of application products on the user side.
●Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
(3)
Port state immediately after reset
Table 3.3.1 shows the each pin state during RESET pin is “L”.
Table 3.3.1 Each pin state during RESET pin is “L”
Pin name
P0, P1 (SEG26–SEG39)
P2, P41–P47, P5, P6
P3 (SEG18–SEG25)
P70
P40, P71–P77
SEG0–SEG17
COM0–COM3
Pin state
Input mode (with pull-up)
Input mode (high-impedance)
Pulled up to Vcc level
High-impedance
Input mode (high-impedance)
Vcc level output
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