Rev.2.00
May. 24, 2006
page 67 of 90
REJ03B0028-0200
3826 Group (A version)
Table 22 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
2
100
1000/(4Vcc-8)
40
45
40
45
200
1000/(2Vcc-4)
85
105
85
105
80
800
370
220
100
1000
400
200
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
tsu(RXD–SCLK1)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
tsu(RXD–SCLK2)
th(SCLK2–RXD)
Symbol
Parameter
Limits
Min.
s
ns
Unit
Typ.
Max.
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)