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參數(shù)資料
| 型號(hào)： | M38503M2A-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 8.40 X 17.50 MM, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 33/59頁 |
| 文件大?。?/td> | 885K |
| 代理商： | M38503M2A-XXXFP |
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Rev.2.13
Apr 17, 2009
Page 39 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
[MISRG (MISRG)] 003816
MISRG consists of three control bits (bits 1 to 3) for middle-
speed mode automatic switch and one control bit (bit 0) for
oscillation stabilizing time set after STP instruction released.
By setting the middle-speed mode automatic switch start bit to
“1” while operating in the low-speed mode and setting the
middle-speed mode automatic switch set bit to “1”, XIN
oscillation automatically starts and the mode is automatically
switched to the middle-speed mode.
Fig 44. Structure of MISRG
Fig 45. System clock generating circuit block diagram (Single-chip mode)
MISRG
(MISRG : address 003816)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 6.5 to 7.5 machine cycles
1: 4.5 to 5.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
b7
b0
Note: When the mode is automatically switched from the low-speed mode to the
middle-speed mode, the value of CPU mode register (address 003B16)
changes.
WIT
instruction
STP
instruction
Timing
φ (internal clock)
S
R
Q
S
R
Q
Main clock stop bit
S
R
Q
1/2
1/4
XIN
XOUT
XCOUT
XCIN
Interrupt request
Interrupt disable flag l
Reset
1/2
Port XC
switch bit
“1”
“0”
low-speed mode
High-speed or
middle-speed mode
Middle-speed mode
High-speed or
Low-speed mode
Main clock division ratio
selection bits (Note 1)
Main clock division ratio
selection bits (Note 1)
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port XC switch bit (b4) to “1”.
2:f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the STP instruction is supplied as the
count source at executing STP instruction.
3: When bit 0 of MISRG = “0”, the prescaler 12 is set to “FF16” and timer 1 is set to “0116”.
When bit 0 of MISRG = “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1.
4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
Prescaler 12
Timer 1
Reset or
STP instruction
(Note 2)
Reset
(Note 3)
Timer 12 count
source selection bit
(Note 4)
STP
instruction
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