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參數(shù)資料
| 型號(hào)： | M38503M2A-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 8.40 X 17.50 MM, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 50/59頁 |
| 文件大?。?/td> | 885K |
| 代理商： | M38503M2A-XXXFP |
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Rev.2.13
Apr 17, 2009
Page 54 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
2. Notes when selecting clock asynchronous serial I/O
(Serial I/O1)
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to
“0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as
I/O ports, the transmission data is not output). When data is
written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O1
enable bit is set to “1” at this time, the data during internally
shifting is output to the TxD pin and an operation failure occurs.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to
“0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as
I/O ports, the transmission data is not output). When data is
written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O1
enable bit is set to “1” at this time, the data during internally
shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
3. Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission
and the reception circuits are reset by clearing both the transmit
enable bit and the receive enable bit to “0”.
Fig 54. Sequence of setting serial I/O1 control register
again
4. Data transmission control with referring to transmit
shift register completion flag (Serial I/O1)
The transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after writing
the data to the transmit buffer register, note the delay.
5. Transmit interrupt request when transmit enable bit
is set (Serial I/O1)
When the transmit interrupt is used, set the transmit interrupt
enable bit to transmit enabled as shown in the following
sequence.
(1) Set the interrupt enable bit to “0” (disabled) with CLB
instruction.
(2) Prepare serial I/O for transmission/reception.
(3) Set the interrupt request bit to “0” with CLB instruction
after 1 or more instruction has been executed.
(4) Set the interrupt enable bit to “1” (enabled).
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer
empty flag and transmit shift register completion flag are set to
“1”.
The interrupt request is generated and the transmission interrupt
request bit is set regardless of which of the two timings listed
below is selected as the timing for the transmission interrupt to
be generated.
Transmit buffer empty flag is set to “1”
Transmit shift register completion flag is set to “1”
6. Transmission
control
when
external
clock
is
selected (Serial I/O1 clock synchronous mode)
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the
SCLK1 input level. Also, write the transmit data to the transmit
buffer register (serial I/O shift register) at “H” of the SCLK1 input
level.
7. Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external
clock as synchronous clock, write the transmit data to the serial
I/O2 register (serial I/O shift register) at “H” of the transfer clock
input level.
Notes on PWM
The PWM starts after the PWM enable bit is set to enable and
“L” level is output from the PWM pin.
The length of this “L” level output is as follows:
n + 1
2
× f(XIN)
(s)
(Count source selection bit = “0”,
where n is the value set in the prescaler)
n + 1
f(XIN)
(s)
(Count source selection bit = “1”,
where n is the value set in the prescaler)
Can be set with the
LDM instruction at
the same time
Set the bits 0 to 3 and bit 6 of the serial I/O1
control register
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to “0”
Set both the transmit enable bit (TE) and the
receive enable bit (RE), or one of them to “1”
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