- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370954 > M38869FFAGP (Mitsubishi Electric Corporation) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PDF資料下載
參數(shù)資料
| 型號(hào)： | M38869FFAGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 46/110頁(yè) |
| 文件大?。?/td> | 1601K |
| 代理商： | M38869FFAGP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)當(dāng)前第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)
46
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
+ 2 cycles (3.375
μ
s)
+ 1 cycle < 4.0
μ
s (3.25
μ
s)
Fig. 43 START condition detecting timing diagram
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 43, 44, and Table 13. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the S
CL
and S
DA
pins satisfy three conditions: S
CL
re-
lease time, setup time, and hold time (see Table 13).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 13, the BB flag set/
reset time.
Note:
When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “I
2
CIRQ” occurs to the CPU.
Table 13 START condition/STOP condition detecting conditions
Note:
Unit : Cycle number of system clock
φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I
2
C START/
STOP condition control register is set to “18
16
” at
φ
= 4 MHz.
Fig. 44 STOP condition detecting timing diagram
S
CL
release time
Standard clock mode
SSC value + 1 cycle (6.25
μ
s)
High-speed clock mode
4 cycles (1.0
μ
s)
2 cycles (1.0
μ
s)
2 cycles (0.5
μ
s)
3.5 cycles (0.875
μ
s)
SSC value
2
SSC value
2
SSC value –1
2
Setup time
Hold time
BB flag set/
reset time
cycle < 4.0
μ
s (3.0
μ
s)
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I
2
C status
register (address 0014
16
) at the same time after writing the slave
address to the I
2
C data shift register (address 0012
16
) with the
condition in which the ES0 bit of the I
2
C control register (address
0015
16
) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “000
2
” and an S
CL
for 1 byte is out-
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 41, the START condition generating timing diagram, and
Table 11, the START condition generating timing table.
STOP Condition Generating Method
When the ES0 bit of the I
2
C control register (address 0015
16
) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I
2
C status register (address 0014
16
) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 42, the STOP condition generating timing
diagram, and Table 12, the STOP condition generating timing
table.
Fig. 41 START condition generating timing diagram
Fig. 42 STOP condition generating timing diagram
Table 12 STOP condition generating timing table
Item
Setup
time
START/STOP condition
generating selection bit
“0”
“1”
“0”
“1”
Standard
clock mode
5.5
μ
s (22 cycles)
13.5
μ
s (54 cycles)
5.5
μ
s (22 cycles)
13.5
μ
s (54 cycles)
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses denotes the
number of
φ
cycles.
High-speed
clock mode
3.0
μ
s (12 cycles)
7.0
μ
s (28 cycles)
3.0
μ
s (12 cycles)
7.0
μ
s (28 cycles)
Table 11 START condition generating timing table
Item
Setup
time
START/STOP condition
generating selection bit
“0”
“1”
“0”
“1”
Standard
clock mode
5.0
μ
s (20 cycles)
13.0
μ
s (52 cycles)
5.0
μ
s (20 cycles)
13.0
μ
s (52 cycles)
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses denotes the
number of
φ
cycles.
High-speed
clock mode
2.5
μ
s (10 cycles)
6.5
μ
s (26 cycles)
2.5
μ
s (10 cycles)
6.5
μ
s (26 cycles)
Hold
time
Hold
time
I
2
C
w
t
s
e
t
a
s
t
g
u
s
n
r
l
e
g
i
s
t
e
r
r
i
i
a
H
o
l
d
t
i
m
e
S
e
t
t
u
e
p
i
m
S
C
L
S
D
A
I
2
C
w
t
s
e
t
a
s
t
g
u
s
n
r
l
e
g
i
s
t
e
r
r
i
i
a
H
o
l
d
t
i
m
e
S
e
t
t
u
e
p
i
m
S
C
L
S
D
A
H
o
l
d
t
i
m
e
S
e
t
t
u
e
p
i
m
S
C
L
S
D
A
B
f
l
a
g
S
C
L
r
e
l
e
a
s
e
t
i
m
e
B
r
e
t
i
B
s
m
e
e
f
l
t
a
g
H
o
l
d
t
i
m
e
S
e
t
t
u
e
p
i
m
S
C
L
S
D
A
B
f
l
a
g
S
C
L
r
e
l
e
a
s
e
t
i
m
e
B
r
e
t
i
B
s
m
e
e
f
l
t
a
g
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M38867M8A | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38867M8A-010HP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38867M8A-011HP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869MCA-XXXGP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869MCA-XXXHP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38869FFAGP#U0 | 功能描述:IC 740/3886 MCU FLASH 80QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標(biāo)準(zhǔn)包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外圍設(shè)備:DMA，POR，PWM，WDT 輸入/輸出數(shù):121 程序存儲(chǔ)器容量:384KB（384K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b，D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤(pán) 產(chǎn)品目錄頁(yè)面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
| M38869FFAHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869FFAHP#UU | 功能描述:IC 740/3886 MCU FLASH 80LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標(biāo)準(zhǔn)包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外圍設(shè)備:DMA，POR，PWM，WDT 輸入/輸出數(shù):121 程序存儲(chǔ)器容量:384KB（384K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b，D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤(pán) 產(chǎn)品目錄頁(yè)面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
| M38869FF-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869M1-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。