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參數(shù)資料
| 型號(hào)： | M38869FFAGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 54/110頁 |
| 文件大小： | 1601K |
| 代理商： | M38869FFAGP |
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54
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
COMPARATOR CIRCUIT
Comparator Configuration
The comparator circuit consists of resistors, comparators, a com-
parator control circuit, the comparator reference input selection bit
(bit 7 of address 001D
16
), a comparator data register (address
002D
16
), the comparator reference power source input pin (P0
0
/
P3
REF
) and analog signal input pins (P3
0
–P3
7
). The analog input
pin (P3
0
–P3
7
) also functions as an ordinary digital port.
Comparator Operation
To activate the comparator, first set port P3 to input mode by set-
ting the corresponding direction register (address 0007
16
) to “0” to
use port P3 as an analog voltage input pin. The internal fixed ana-
log voltage (V
CC
29/32) can be generated by setting “1” to the
comparator reference input selection bit (bit 7) of the serial I/O2
control register (address 001D
16
). (The internal fixed analog volt-
age becomes about 4.5 V at V
CC
= 5.0 V.) When setting “0” to the
comparator reference input selection bit, the P0
0
/P3
REF
pin be-
comes the comparator reference power source input pin and it is
possible to input the comparator reference power source option-
ally from the external. The voltage comparison is immediately
performed by the writing operation to the comparator data register
(address 002D
16
). After 14 cycles of the internal system clock
φ
(the time required for the comparison), the comparison result is
stored in the comparator register (address 002D
16
).
If the analog input voltage is greater than the internal reference
voltage, each bit of this register is “1”; if it is less than the internal
reference voltage, each bit of this register is “0”. To perform an-
other comparison, the voltage comparison must be performed
again by writing to the comparator data register (address 002D
16
).
Read the result when 14 cycles of
φ
or more have passed after the
comparator operation starts. The ladder resistor is turned on dur-
ing 14 cycles of
φ
, which is required for the comparison, and the
reference voltage is generated. An unnecessary current is not
consumed because the ladder resistor is turned off while the com-
parator operation is not performed. Since the comparator consists
of capacitor coupling, the electric charge is lost if the clock fre-
quency is low.
Keep that the clock frequency is 1 MHz or more during the com-
parator operation. Do not execute the STP, WIT, or port P3 I/O
instruction.
Fig. 52 Comparator circuit
V
S
S
8
8
V
C
C
P
3
(
8
)
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3
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3
6
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