Rev.3.02
Apr 10, 2008
REJ03B0177-0302
38D2 Group
Fig. 58 Internal status at reset
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
001016
001116
001216
001316
001416
001516
001916
001A16
001B16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
Address
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
0FF016
0FF116
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
(PS)
(PCH)
(PCL)
Port P0
Port P0 direction register
Port P1
Port P1 direction register
Port P2
Port P2 direction register
Port P3
Port P3 direction register
Port P4
Port P4 direction register
Port P5
Port P5 direction register
Port P6
Port P6 direction register
Oscillation output control register
CPU mode register 2
RRF register
LCD mode register
LCD power control register
AD control register
Serial I/O1 status register
Serial I/O1 control register
UART1 control register
Serial I/O2 status register
Serial I/O2 control register
Timer 1
Timer 2
Timer 3
Timer 4
PWM01 register
Timer 12 mode register
Timer 34 mode register
Timer 1234 mode register
Timer 1234 frequency division
selection register
Watchdog timer control register
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
Timer X (low-order)
Timer X (high-order)
Timer X (extension)
Timer X mode register
Timer X control register 1
Timer X control register 2
Compare register 1 (low-order)
Compare register 1 (high-order)
Compare register 2 (low-order)
Compare register 2 (high-order)
Compare register 3 (low-order)
Compare register 3 (high-order)
Timer Y (low-order)
Timer Y (high-order)
Timer Y mode register
Timer Y control register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
PULL register
UART2 control register
Clock output control register
Segment output disable register 0
Segment output disable register 1
Segment output disable register 2
Key input control register
ROM correction address 1
high-order register (RCA1H)
ROM correction address 1
low-order register (RCA1L)
ROM correction address 2
high-order register (RCA2H)
ROM correction address 2
low-order register (RC2AL)
ROM correction enable register
Processor status register
Program counter
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
(67)
(68)
(69)
(70)
(71)
0016
Register contents
0016
0816
0016
FF16
0116
FF16
0016
Address
000 00
0*
0
0 0011
1 1
1
10000
00
0
1 1100
0 0
0
FF16
0016
FF16
0016
FF16
0016
Register contents
*1 *0 0
0 0
0
×
1
FFFD16 contents
FFFC16 contents
1 0000
0 0
0
111 0 0
00
0
×× × ×
× ×
×: Not fixed
*: Depends on OSCSEL setting at the QzROM version.
In the flash memory version, the CPU mode register 2 (address 001116), is set to “0016” and the CPU mode register (address 003B16) is set to “E016”.
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.