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參數(shù)資料
| 型號(hào)： | M390S3323DT1-C7A |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | M390S3323DT1-C7A |
M390S3323DT1
PC133 Registered DIMM
Rev. 0.1 Sept. 2001
M390S3323DT1-C7C/C7A
Organization : 32MX72
Composition : 16MX8 *18
Used component part # : K4S280832D-TC7C/TC75
# of rows in module : 2 Rows
# of banks in component : 4 banks
Feature : 1,700 mil height & double sided component
Refresh : 4K/64ms
Contents :
Byte #
Function described
Function Supported
Hex value
Note
-7C
-7A
-7C
-7A
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
12
0Ch
1
4
# of column address on this assembly
10
0Ah
1
5
# of module Rows on this assembly
2 Row
02h
6
Data width of this assembly
72 bits
48h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time from clock @CAS latency of 3
7.5ns
75h
2
10
SDRAM access time from clock @CAS latency of 3
5.4ns
54h
2
11
DIMM configuration type
ECC
02h
12
Refresh rate & type
15.625us, support self refresh
80h
13
Primary SDRAM width
x8
08h
14
Error checking SDRAM width
x8
08h
15
Minimum clock delay for back-to-back random column address
tCCD = 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4 , 8 and full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Registered/Buffered DQM,
address & control inputs and
On-card PLL
1Fh
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
7.5ns
10ns
75h
A0h
2
24
SDRAM access time @CAS latency of 2
5.4ns
6ns
54h
60h
2
25
SDRAM cycle time @CAS latency of 1
-
00h
2
26
SDRAM access time @CAS latency of 1
-
00h
2
27
Minimum row precharge time (=tRP)
15ns
20ns
0Fh
14h
28
Minimum row active to row active delay (t RRD)
15ns
0Fh
29
Minimum RAS to CAS delay (=tRCD)
15ns
20ns
0Fh
14h
30
Minimum activate precharge time (=tRAS)
45ns
2Dh
31
Module Row density
2 Row of 128MB
20h
32
Command and Address signal input setup time
1.5 ns
15h
33
Command and Address signal input hold time
0.8 ns
08h
34
Data signal input setup time
1.5 ns
15h
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M390S6450CT1 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD |
| M390S6450CT1-C7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD |
| M390S6450CT1-C7C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD |
| M390S6450ET1-C7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:168pin Registered Module based on 256Mb E-die with 72-bit ECC |
| M390S6450ET1-C7A00 | 制造商:Samsung 功能描述:256 SDRAM MODULE X72 TSOP2-400 - Trays |
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