參數(shù)資料
型號(hào)： M393B1K73CH0-YH9
元件分類： DRAM
英文描述： 1G X 72 MULTI DEVICE DRAM MODULE, 0.255 ns, DMA240
封裝： HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
文件頁(yè)數(shù)： 17/53頁(yè)
文件大小： 1492K
代理商： M393B1K73CH0-YH9
- 17 -
datasheet
DDR3L SDRAM
Rev. 1.01
Registered DIMM
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. Single ended swing requirement for DQS - DQS is 350mV (peak to peak). Differential swing requirement for DQS - DQS is 700mV (peak to peak).
13.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage
VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of VREF. Fur-
thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure 1.
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise.
Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
voltage
VDD
VSS
time
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