- 15 -
datasheet
DDR3L SDRAM
Rev. 1.01
Registered DIMM
VSS
VDD
D0 - D35
VREFCA
VDDSPD
Serial PD
VTT
VREFDQ
D0 - D35
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL
SDA
DQS14
VSS
CB[47:44]
DQS
DM
DQ[3:0]
D14
CS RA
S
CA
S
WE CK
CK
E
ODT
A[N
:0
]/B
A[N
:0
]
RS
0B
RR
AS
B
RC
AS
B
RW
E
B
PC
K0
B
PC
K0
B
RC
KE
0B
RODT0
B
A[N
:0
]B
/BA
[N:0]
B
D32
CS RA
S
CA
S
WE CK CK
CK
E
ODT A[N
:0
]/B
A[N
:0
]
RS
1B
PC
K1
B
PC
K1
B
RC
KE
1B
RODT1
B
DQS
DM
DQ[3:0]
DQS4
VSS
DQ[35:32]
DQS
DM
DQ[3:0]
D4
CS RA
S
CA
S
WE CK
CK
E
ODT
A
[N
:0]/
BA[
N:
0]
D22
CS RA
S
CA
S
WE CK CK
CK
E
ODT A
[N
:0]/
BA[
N:
0]
DQS
DM
DQ[3:0]
DQS16
VSS
DQ[63:60]
DQS
DM
DQ[3:0]
D16
CS RAS CAS WE CK
CK
CKE OD
T
A[
N:
0]
/B
A[
N:
0
]
D34
CS RAS CAS WE CK CK
CKE
OD
T
A[
N:
0]
/B
A[
N:
0
]
DQS
DM
DQ[3:0]
DQS10
VSS
DQ[59:56]
DQS
DM
DQ[3:0]
D7
CS RA
S
CA
S
WE CK
CK
E
ODT
A[N
:0
]/B
A[N
:0
]
D25
CS RA
S
CA
S
WE CK CK
CK
E
ODT A[N
:0
]/B
A[N
:0
]
DQS
DM
DQ[3:0]
Vtt
DQS13
VSS
CB[39:36]
DQS
DM
DQ[3:0]
D13
CS RA
S
CA
S
WE CK CK
CK
E
ODT A[N
:0
]/B
A[N
:0
]
RS
0B
RR
AS
B
RC
AS
B
RW
E
B
PC
K0
B
PC
K0
B
RC
KE
0B
RODT0
B
A[N
:0
]B
/BA
[N:0]
B
D31
CS RA
S
CA
S
WE CK CK
CK
E
ODT A[N
:0
]/B
A[N
:0
]
RS
1B
PC
K1
B
PC
K1
B
RC
KE
1B
RODT1
B
DQS
DM
DQ[3:0]
DQS5
VSS
DQ[43:40]
DQS
DM
DQ[3:0]
D5
CS RA
S
CA
S
WE CK CK
CK
E
ODT A
[N
:0]/
BA[
N:
0]
D23
CS RA
S
CA
S
WE CK CK
CK
E
ODT A
[N
:0]/
BA[
N:
0]
DQS
DM
DQ[3:0]
DQS15
VSS
DQ[55:52]
DQS
DM
DQ[3:0]
D15
CS RAS CAS WE CK CK
CKE
OD
T
A[
N:
0]
/B
A[
N:
0
]
D33
CS RAS CAS WE CK CK
CKE
OD
T
A[
N:
0]
/B
A[
N:
0
]
DQS
DM
DQ[3:0]
DQS6
VSS
DQ[51:48]
DQS
DM
DQ[3:0]
D6
CS RA
S
CA
S
WE CK CK
CK
E
ODT A[N
:0
]/B
A[N
:0
]
D24
CS RA
S
CA
S
WE CK CK
CK
E
ODT A[N
:0
]/B
A[N
:0
]
DQS
DM
DQ[3:0]
Vtt
Option 1
A0
Thermal sensor
A1 A2
SA0 SA1 SA2
SCL
SDA
EVENT
WP
Serial PD w/ stand alone Thermal sensor
A0
Integrated Thermal sensor in SPD
A1 A2
SA0 SA1 SA2
SCL
SDA
EVENT
Option 2
Serial PD w/ integrated Thermal sensor
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL
SDA
Option 3
Serial PD, no Thermal sensor
WP
NOTE:
1. DQ-to-I/O wiring may be changed within a nibble.
2. See wiring diagrams for resistor values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240 +/-1%)ohms...
1:2
R
E
G
I
S
T
E
R
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
RESET
RST : SDRAMs D[35:0]
PAR_IN
S0
RS0A -> CS0 : SDRAMs D[3:0], D[12:0], D17
ERR_OUT
RST
CK0
ODT0
CK0
RS0B -> CS0 : SDRAMs D[7:4], D[16:13]
RS1A -> CS1 : SDRAMs D[21:18], D[30:26], D35
RS1B -> CS1 : SDRAMs D[25:22], D[34:31]
RBA[N:0]A -> BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RBA[N:0]B -> BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RA[N:0]A -> A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RA[N:0]B -> A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RRASA -> RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASB -> RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA -> CAS: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
RCASB -> CAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
RWEA -> WE: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
RWEB -> WE: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
RCKE0A -> CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B -> CKE0: SDRAMs D[7:4], D[16:13]
RODT0A -> ODT0: SDRAMs D[3:0], D[12:8], D17
RODT0B -> ODT0: SDRAMs D[7:4], D[16:13]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4], D[16:13]
PCK1A -> CK: SDRAMs D[21:18], D[30:26], D35
PCK1B -> CK: SDRAMs D[25:22], D[34:31]
S1
CKE1
RCKE1A -> CKE1: SDRAMs D[21:18], D[30:26], D35
RCKE1B -> CKE1: SDRAMs D[25:22], D[34:31]
ODT1
RODT1A -> ODT1: SDRAMs D[21:18], D[30:26], D35
RODT1B -> ODT1: SDRAMs D[25:22], D[34:31]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4], D[16:13]
PCK1A -> CK: SDRAMs D[21:18], D[30:26], D35
PCK1B -> CK: SDRAMs D[25:22], D[34:31]
CK0
120
Ω
±3%