參數(shù)資料
型號(hào): M393B1K73CH0-YH9
元件分類: DRAM
英文描述: 1G X 72 MULTI DEVICE DRAM MODULE, 0.255 ns, DMA240
封裝: HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
文件頁(yè)數(shù): 22/53頁(yè)
文件大?。?/td> 1492K
代理商: M393B1K73CH0-YH9
- 22 -
datasheet
DDR3L SDRAM
Rev. 1.01
Registered DIMM
Figure 6. Single-ended output slew rate definition
14.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOH-
diff(AC) for differential signals as shown in below.
[ Table 12 ] Differential Output slew rate definition
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 13 ] Differential Output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Single-ended Signals
For Ron = RZQ/7 setting
Figure 7. Differential output slew rate definition
Description
Measured
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
VOHdiff(AC)-VOLdiff(AC)
Delta TRdiff
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
VOHdiff(AC)-VOLdiff(AC)
Delta TFdiff
Parameter
Symbol
Operation
Voltage
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Min
Max
Min
Max
Min
Max
Min
Max
Single ended output slew rate
SRQse
1.35V
3.5
10
3.5
10
-
TBD
V/ns
1.5V
5
10
5
10
5
10
TBD
10
V/ns
VOHdiff(AC)
VOLdiff(AC)
delta
TRdiff
delta
TFdiff
VTT
VOHdiff(AC)
VOLdiff(AC)
delta
TRdiff
delta
TFdiff
VTT
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