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參數(shù)資料
| 型號： | M393B1K73CH0-YH9 |
| 元件分類： | DRAM |
| 英文描述： | 1G X 72 MULTI DEVICE DRAM MODULE, 0.255 ns, DMA240 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 21/53頁 |
| 文件大?。?/td> | 1492K |
| 代理商： | M393B1K73CH0-YH9 |
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datasheet
DDR3L SDRAM
Rev. 1.01
Registered DIMM
14. AC & DC Output Measurement Levels
14.1 Single Ended AC and DC Output Levels
[ Table 8 ] Single Ended AC and DC output levels
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25
Ω to VTT=VDDQ/2.
14.2 Differential AC and DC Output Levels
[ Table 9 ] Differential AC and DC output levels
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25
Ω to VTT=VDDQ/2 at each of the differential outputs.
14.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
[ Table 10 ] Single ended Output slew rate definition
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 11 ] Single ended output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals, For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ
signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the
remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOH(DC) DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOM(DC) DC output mid measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOL(DC) DC output low measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC) AC output high measurement level (for output SR)
VTT + 0.1 x VDDQ
V1
VOL(AC) AC output low measurement level (for output SR)
VTT - 0.1 x VDDQ
V1
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V1
Description
Measured
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
VOH(AC)-VOL(AC)
Delta TRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
VOH(AC)-VOL(AC)
Delta TFse
Parameter
Symbol
Operation
Voltage
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Min
Max
Min
Max
Min
Max
Min
Max
Single ended output slew rate
SRQse
1.35V
1.75
51)
1.75
51)
-
TBD
V/ns
1.5V
2.5
5
2.5
5
2.5
5
TBD
5
V/ns
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