參數(shù)資料
型號(hào): M48ST59W-70MH1TR
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封裝: 0.330 INCH, SNAPHAT, PLASTIC, SOH-44
文件頁(yè)數(shù): 10/29頁(yè)
文件大?。?/td> 158K
代理商: M48ST59W-70MH1TR
M48ST59W
18/29
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE Bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48ST59W was in the deselect mode
during power-up. Figure 10 illustrates the back-up
mode alarm timing.
Programmable Interrupts
The M48ST59W provides two programmable in-
terrupts; an alarm and a watchdog. When an inter-
rupt condition occurs, the M48ST59W sets the
appropriate flag bit in the Flag Register 1FF0h.
The interrupt enable Bits (AFE and ABE) in 1FF6h
and the Watchdog Steering Bit (WDS) in 1FF7h al-
low the interrupt to activate the IRQ/FT pin.
The interrupt flags and the IRQ/FT output are
cleared by a READ to the Flags Register. An inter-
rupt condition reset will not occur unless the ad-
dresses are stable at the flag location for at least
15ns while the device is in the READ Mode (see
Figure 11, page 19).
The IRQ/FT pin is an open drain output and re-
quires a pull-up resistor (10k
recommended) to
VCC. The pin remains in the high impedance state
unless an interrupt occurs or the frequency test
mode is enabled.
Table 12. Alarm Repeat Mode
Figure 10. Back-up Mode Alarm Waveform
RPT4
RPT3
RPT2
RPT1
Alarm Activated
1
Once per Second
1
0
Once per Minute
1
0
Once per Hour
1
0
Once per Day
0
Once per Month
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
HIGH-Z
IRQ/FT
HIGH-Z
tREC
VCC
VPFD (max)
VPFD (min)
VSO
AI04610
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