參數(shù)資料
型號(hào)： M48ST59W-70MH1TR
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO44
封裝： 0.330 INCH, SNAPHAT, PLASTIC, SOH-44
文件頁(yè)數(shù)： 2/29頁(yè)
文件大小： 158K
代理商： M48ST59W-70MH1TR
M48ST59W
10/29
READ Mode
The M48ST59W is in the READ Mode whenever
WRITE Enable (W) is high and Chip Enable (E) is
low. The unique address specified by the 13 Ad-
dress Inputs defines which one of the 8,176 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
Time (tAVQV) after the last address input signal is
stable, providing that the E and Output Enable (G)
access times are also satisfied. If the E and G ac-
cess times are not met, valid data will be available
after the latter of the Chip Enable Access Time
(tELQV) or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
Time (tAXQX) but will be indeterminate until the
next Address Access.
Figure 6. READ Mode AC Waveforms
Table 7. READ Mode AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA =0 to 70°Cor –40 to 85°C; VCC = 2.7 to 3.6V (except where noted).
2. CL = 5 pF.
Symbol
Parameter(1)
M48ST59W
Unit
–70 / –100
Min
Max
tAVAV
READ Cycle Time
70
ns
tAVQV
Address Valid to Output Valid
70
ns
tELQV
Chip Enable Low to Output Valid
70
ns
tGLQV
Output Enable Low to Output Valid
35
ns
tELQX
(2)
Chip Enable Low to Output Transition
5
ns
tGLQX
(2)
Output Enable Low to Output Transition
5
ns
tEHQZ
(2)
Chip Enable High to Output Hi-Z
25
ns
tGHQZ
(2)
Output Enable High to Output Hi-Z
25
ns
tAXQX
Address Transition to Output Transition
10
ns
VALID
A0-A12
E
G
DQ0-DQ7
VALID
tAVAV
tAVQV
tELQV
tAXQX
tEHQX
tELQX
tGLQV
tGHQZ
tGLQX
AI04606
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