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參數(shù)資料
| 型號： | M48ST59W-70MH1TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封裝： | 0.330 INCH, SNAPHAT, PLASTIC, SOH-44 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大小： | 158K |
| 代理商： | M48ST59W-70MH1TR |
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M48ST59W
Calibrating the Clock
The M48ST59W is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are tested not to exceed 35 ppm
(parts per million) oscillator frequency error at
25
°C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48ST59W improves to better
than +1/–2 ppm at 25
°C.
The oscillation rate of any crystal changes with
temperature (see Figure 15, page 23). Most clock
chips compensate for crystal frequency and tem-
perature shift error with cumbersome trim capaci-
tors. The M48ST59W design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage (see Figure 16,
page 23). The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five-bit Calibration byte found in the
Control Register. Adding counts speeds the clock
up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control register (1FF8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; ’1’ indi-
cates positive calibration, ’0’ indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary ’1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles; for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48ST59W may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his en-
vironment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz when the
Stop Bit (D7 of 1FF9h) is ’0’, the FT Bit (D6 of
1FFCh) is ’1,’ the AFE Bit (D7 of 1FF6h) is ’0’, and
the Watchdog Steering Bit (D7 of 1FF7h) is ’1’ or
the Watchdog Register is reset (1FF7h = 0).
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 ppm oscillator frequency
error, requiring a –10 (WR001010) to be loaded
into the Calibration Byte for correction. Note that
setting or changing the Calibration Byte does not
affect the Frequency test output frequency.
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor for proper operation. A
500-10k
resistor is recommended in order to
control the rise time. The FT Bit is cleared on pow-
er-down.
Note: For more information on calibration, see the
Application Note AN934, “TIMEKEEPER Calibra-
tion.”
Setting Alarm Clock
Registers 1FF5h-1FF2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific day of the month or
repeat every month, day, hour, minute, or second.
It can also be programmed to go off while the
M48ST59W is in the battery back-up mode of op-
eration to serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Possible configurations are shown in
Table 12. Codes not listed in the table default to
the once per second mode to quickly alert the user
of an incorrect alarm setting.
Note: The user must transition address (or toggle
chip enable) to see the Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ‘0’ to the Alarm Date register and RPT1-4.
The alarm flag and the IRQ/FT output are cleared
by a READ to the Flags Register.
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