- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄229296 > M48Z12-70PC6 (STMICROELECTRONICS) 2K X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP24 PDF資料下載
參數(shù)資料
| 型號： | M48Z12-70PC6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP24 |
| 封裝： | 0.600 INCH, ROHS COMPLIANT, CAPHAT, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 19/21頁 |
| 文件大?。?/td> | 177K |
| 代理商： | M48Z12-70PC6 |
M48Z02, M48Z12
Operation modes
2
Operation modes
The M48Z02/12 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below
approximately 3 V, the control circuitry connects the battery which maintains data operation
until valid power returns.
Table 2.
Operating modes
Note:
X = VIH or VIL; VSO = Battery backup switchover voltage.
2.1
Read mode
The M48Z02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (tAVQV) after the last
address input signal is stable, providing that the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the chip
enable access time (tELQV) or output enable access time (tGLQV).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (tAXQX) but will go indeterminate until the next address access.
Mode
VCC
E
G
W
DQ0-
DQ7
Power
Deselect
4.75 to 5.5 V
or
4.5 to 5.5 V
VIH
X
High Z
Standby
WRITE
VIL
XVIL
DIN
Active
READ
VIL
VIH
DOUT
Active
READ
VIL
VIH
High Z
Active
Deselect
VSO to VPFD(min)
(1)
1.
See Table 10 on page 16 for details.
X
High Z
CMOS standby
Deselect
≤ VSO(1)
X
High Z
Battery backup mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT48V8M16LFF4-10XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT55L256V36PT-6 | 256K X 36 ZBT SRAM, 3.5 ns, PQFP100 |
| MT5C2561EC-45IT | 256K X 1 STANDARD SRAM, 45 ns, CQCC28 |
| M378T3253FG0-CE6 | 32M X 64 DDR DRAM MODULE, 0.45 ns, DMA240 |
| M93C06-DS3TG | 16 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z12-70PC6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z128 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER? SRAM |
| M48Z128-120CS1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128-120PM1 | 功能描述:NVRAM 1M (128Kx8) 120ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。