參數(shù)資料
型號: M48Z12-70PC6
廠商: STMICROELECTRONICS
元件分類: SRAM
英文描述: 2K X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP24
封裝: 0.600 INCH, ROHS COMPLIANT, CAPHAT, PLASTIC, DIP-24
文件頁數(shù): 20/21頁
文件大小: 177K
代理商: M48Z12-70PC6
Operation modes
M48Z02, M48Z12
Figure 4.
Read mode AC waveforms
Note:
WRITE enable (W) = high.
Table 3.
Read mode AC characteristics
2.2
Write mode
The M48Z02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior
to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the
end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ after W falls.
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
M48Z02/M48Z12
Unit
–70
–150
–200
Min
Max
Min
Max
Min
Max
tAVAV
READ cycle time
70
150
200
ns
tAVQV
Address valid to output valid
70
150
200
ns
tELQV
Chip enable low to output valid
70
150
200
ns
tGLQV
Output enable low to output valid
35
75
80
ns
tELQX
Chip enable low to output transition
5
10
ns
tGLQX
Output enable low to output transition
5
ns
tEHQZ
Chip enable high to output Hi-Z
25
35
40
ns
tGHQZ
Output enable high to output Hi-Z
25
35
40
ns
tAXQX
Address transition to output transition
10
5
ns
AI01330
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A10
E
G
DQ0-DQ7
VALID
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