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參數(shù)資料
| 型號： | M48Z12-70PC6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP24 |
| 封裝： | 0.600 INCH, ROHS COMPLIANT, CAPHAT, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大小： | 177K |
| 代理商： | M48Z12-70PC6 |
Operation modes
M48Z02, M48Z12
Table 4.
Write mode AC characteristics
2.3
Data retention mode
With valid VCC applied, the M48Z02/12 operates as a conventional BYTEWIDE static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48Z02/12 may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
The power switching circuit connects external VCC to the RAM and disconnects the battery
when VCC rises above VSO. As VCC rises, the battery voltage is checked. If the voltage is too
low, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked after
power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is
automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 7
on page 11 illustrates how a BOK check routine could be structured.
For more information on a battery storage life refer to the application note AN1012.
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
M48Z02/M48Z12
Unit
–70
–150
–200
Min
Max
Min
Max
Min
Max
tAVAV
WRITE cycle time
70
150
200
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable 1 low
0
ns
tWLWH
WRITE enable pulse width
50
90
120
ns
tELEH
Chip enable low to chip enable 1 high
55
90
120
ns
tWHAX
WRITE enable high to address transition
0
10
ns
tEHAX
Chip enable high to address transition
0
10
ns
tDVWH
Input valid to WRITE enable high
30
40
60
ns
tDVEH
Input valid to Chip enable high
30
40
60
ns
tWHDX
WRITE enable high to input transition
5
ns
tEHDX
Chip enable high to input transition
5
ns
tWLQZ
WRITE enable low to output Hi-Z
25
50
60
ns
tAVWH
Address valid to WRITE enable high
60
120
140
ns
tAVEH
Address valid to chip enable high
60
120
140
ns
tWHQX
WRITE enable high to output transition
5
10
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z12-70PC6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z128 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER? SRAM |
| M48Z128-120CS1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128-120PM1 | 功能描述:NVRAM 1M (128Kx8) 120ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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