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參數(shù)資料
| 型號(hào)： | M48Z2M1YPL |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 122 x 32 pixel format, Compact LCD size |
| 中文描述： | 16兆的2Mb × 8 ZEROPOWER的SRAM |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | M48Z2M1YPL |
able after the later of Chip Enable Access time
(t
ELQV
) or Output Enable Access Time (t
GLQV
). The
state of the eight three-state Data I/O signals is
controlled by E and G. If the outputs are activated
before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain low, output
data will remain valid for Output Data Hold time
(t
AXQX
) but will go indeterminate until the next Ad-
dress Access.
WRITE MODE
The M48Z2M1/2M1Y is in the Write Mode when-
ever W and E are active. The start of a write is
referenced from the latter occurring falling edge of
W or E. A write is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of t
EHAX
from E or t
WHAX
from W prior to the initiation of
another read or write cycle. Data-in must be valid
t
DVEH
or t
DVWH
prior to the end of write and remain
valid for t
EHDX
or t
WHDX
afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs
t
WLQZ
after W falls.
AI01030
5V
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
1.9k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI02050
INTERNAL
BATTERIES
E
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
2048K x 8
SRAM ARRAY
A0-A20
DQ0-DQ7
W
G
POWER
E
Figure 3. Block Diagram
3/12
M48Z2M1, M48Z2M1Y
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48Z30Y-85PM1 | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30Y-100PM1 | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30 | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30-100PM1 | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30-85PM1 | CMOS 32K x 8 ZEROPOWER SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z30 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30-100PM1 | 制造商:STMicroelectronics 功能描述:NVRAM NVSRAM PARALLEL 256KBIT 5V 28PIN PMDIP - Bulk |
| M48Z30-85PM1 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30PM | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30Y | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
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