參數(shù)資料
型號(hào): M4A3-96/48-55VC
廠(chǎng)商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 25/62頁(yè)
文件大小: 0K
描述: IC CPLD ISP 4A 96MC 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: ispMACH® 4A
可編程類(lèi)型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 5.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
宏單元數(shù): 96
輸入/輸出數(shù): 48
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤(pán)
ispMACH 4A Family
31
BLOCK DIAGRAM – M4A(3,5)-192/96
Central
Switch
Matrix
Block B
I/O88—I/O95
CLK0—CLK3
I/O16—I/O23
Block E
I/O40—I/O47
Block H
I/O32—I/O39
Block G
I0—I15
I/O24—I/O31
Block F
Block A
I/O80—I/O87
Block K
I/O64—I/O71
Block L
I/O72—I/O79
Block C I/O8—I/O15
Block D I/O0—I/O7
I/O56—I/O63 Block J
I/O48—I/O55 Block I
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
68 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
16
4
OE
8
16
8
4
16
24
8
16
34
4
8
24
34
4
8
16
4
16
OE
8
24
34
4
8
16
4
16
OE
8
16
8
4
16
24
8
16
34
4
OE
8
16
8
4
16
24
8
16
4
8
24
4
8
16
4
16
OE
8
24
4
8
16
4
16
OE
4
8
24
16
8
16
8
4
16
OE
4
24
16
8
16
4
8
OE
4
24
16
8
16
4
8
4
8
24
16
8
16
8
4
16
OE
8
16
8
4
16
24
8
16
4
OE
17466G-067
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