參數(shù)資料
型號： M50FW080K5TP
廠商： 意法半導(dǎo)體
英文描述： 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
中文描述： 8兆1兆× 8，統(tǒng)一座3V電源閃存固件集線器
文件頁數(shù)： 13/56頁
文件大?。?/td> 292K
代理商： M50FW080K5TP
M50FW080
Signal descriptions
13/55
2.1.5
Interface configuration (IC)
The Interface Configuration input selects whether the Firmware Hub (FWH) or the
Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be
selected before power-up or during a Reset and, thereafter, cannot be changed. The state
of the Interface Configuration, IC, should not be changed during operation.
To select the Firmware Hub (FWH) Interface the Interface Configuration pin should be left to
float or driven Low, V
IL
; to select the Address/Address Multiplexed (A/A Mux) Interface the
pin should be driven High, V
IH
. An internal pull-down resistor is included with a value of R
IL
;
there will be a leakage current of I
LI2
through each pin when pulled to V
IH
; see
Table 20
.
2.1.6
Interface Reset (RP)
The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP) is
set Low, V
IL
, the memory is in Reset mode: the outputs are put to high impedance and the
current consumption is minimized. When RP is set High, V
IH
, the memory is in normal
operation. After exiting Reset mode, the memory enters Read mode.
2.1.7
CPU Reset (INIT)
The CPU Reset, INIT, pin is used to Reset the memory when the CPU is reset. It behaves
identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
2.1.8
Clock (CLK)
The Clock, CLK, input is used to clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification.
2.1.9
Top Block Lock (TBL)
The Top Block Lock input is used to prevent the Top Block (Block 15) from being changed.
When Top Block Lock, TBL, is set Low, V
IL
, Program and Block Erase operations in the Top
Block have no effect, regardless of the state of the Lock Register. When Top Block Lock,
TBL, is set High, V
IH
, the protection of the Block is determined by the Lock Register. The
state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to
14).
Top Block Lock, TBL, must be set prior to a Program or Block Erase operation is initiated
and must not be changed until the operation completes or unpredictable results may occur.
Care should be taken to avoid unpredictable behavior by changing TBL during Program or
Erase Suspend.
相關(guān)PDF資料
PDF描述
M50FW080N5P 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080N5TP 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB5P 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB5TP 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50LPW002 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M50FW080N 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080N1 功能描述:閃存 3.6V 8M (1Mx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M50FW080N1G 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080N1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080N1TG 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*