![](http://datasheet.mmic.net.cn/330000/M50FW080K5P_datasheet_16433094/M50FW080K5P_30.png)
Status Register
M50FW080
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5.6
Program Suspend status (bit 2)
The Program Suspend Status bit indicates that a Program operation has been suspended
and is waiting to be resumed. The Program Suspend Status should only be considered valid
when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive);
after a Program/Erase Suspend command is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the Program/Erase Controller is active or has
completed its operation; when the bit is ‘1’ a Program/Erase Suspend command has been
issued and the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued the Program Suspend Status bit
returns to ‘0’.
5.7
Block Protection status (bit 1)
The Block Protection Status bit can be used to identify if the Program or Block Erase
operation has tried to modify the contents of a protected block. When the Block Protection
Status bit is to ‘0’ no Program or Block Erase operations have been attempted to protected
blocks since the last Clear Status Register command or hardware reset; when the Block
Protection Status bit is ‘1’ a Program or Block Erase operation has been attempted on a
protected block.
Once it is set to ‘1’ the Block Protection Status bit can only be reset to ‘0’ by a Clear Status
Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new
Program or Block Erase command is issued, otherwise the new command will appear to fail.
Using the A/A Mux Interface the Block Protection Status bit is always ‘0’.
5.7.1
Reserved (Bit 0)
Bit 0 of the Status Register is reserved. Its value should be masked.