參數(shù)資料
型號: M50FW080K5TP
廠商: 意法半導體
英文描述: 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
中文描述: 8兆1兆× 8,統(tǒng)一座3V電源閃存固件集線器
文件頁數(shù): 25/56頁
文件大?。?/td> 292K
代理商: M50FW080K5TP
M50FW080
Command interface
25/55
4.6
Chip Erase command
The Chip Erase Command can be only used in A/A Mux mode to erase the entire chip at a
time. Erasing should not be attempted when V
PP
is not at V
PPH
. The operation can also be
executed if V
PP
is below V
PPH
, but result could be uncertain. Two Bus Write operations are
required to issue the command and start the Program/Erase Controller. Once the command
is issued subsequent Bus Read operations read the Status Register. See the section on the
Status Register for details on the definitions of the Status Register bits. During the Chip
Erase operation the memory will only accept the Read Status Register command. All other
commands will be ignored. Typical Chip Erase times are given in
Table 14
. The Chip Erase
command sets all of the bits in the memory to ‘1’. See
Figure 21
, for a suggested flowchart
on using the Chip Erase command.
4.7
Block Erase command
The Block Erase command can be used to erase a block. Two Bus Write operations are
required to issue the command; the second Bus Write cycle latches the block address in the
internal state machine and starts the Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the Status Register. See the section on the
Status Register for details on the definitions of the Status Register bits.
If the block is protected then the Block Erase operation will abort, the data in the block will
not be changed and the Status Register will output the error.
During the Block Erase operation the memory will only accept the Read Status Register
command and the Program/Erase Suspend command. All other commands will be ignored.
Typical Block Erase times are given in
Table 14
.
The Block Erase command sets all of the bits in the block to ‘1’. All previous data in the block
is lost.
See
Figure 21
, for a suggested flowchart on using the Erase command.
4.8
Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status
Register to ‘0’. One Bus Write is required to issue the Clear Status Register command.
Once the command is issued the memory returns to its previous mode, subsequent Bus
Read operations continue to output the same data.
The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new
Program or Erase command is issued. If an error occurs then it is essential to clear any error
bits in the Status Register by issuing the Clear Status Register command before attempting
a new Program or Erase command.
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M50FW080N5P 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
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