參數(shù)資料
型號(hào)： M50FW080NB5P
廠商： 意法半導(dǎo)體
英文描述： 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
中文描述： 8兆1兆× 8，統(tǒng)一座3V電源閃存固件集線器
文件頁數(shù)： 21/56頁
文件大?。?/td> 292K
代理商： M50FW080NB5P
M50FW080
Bus operations
21/55
Table 5.
Figure 7.
FWH Bus Write waveforms
FWH Bus Write field definitions
Clock
Cycle
Number
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
Description
1
1
START
1110b
I
On the rising edge of CLK with FWH4 Low, the
contents of FWH0-FWH3 indicate the start of a
FWH Write Cycle.
2
1
IDSEL
XXXX
I
Indicates which FWH Flash Memory is selected.
The value on FWH0-FWH3 is compared to the
IDSEL strapping on the FWH Flash Memory pins
to select which FWH Flash Memory is being
addressed.
3-9
7
ADDR
XXXX
I
A 28-bit address phase is transferred starting with
the most significant nibble first.
10
1
MSIZE
0000b
I
Always 0000b (single byte transfer).
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the least
significant nibble.
13
1
TAR
1111b
I
The host drives FWH0-FWH3 to 1111b to indicate
a turnaround cycle.
14
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-
FWH3 during this cycle.
15
1
SYNC
0000b
O
The FWH Flash Memory drives FWH0-FWH3 to
0000b, indicating it has received data or a
command.
16
1
TAR
1111b
O
The FWH Flash Memory drives FWH0-FWH3 to
1111b, indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The FWH Flash Memory floats its outputs and the
host takes control of FWH0-FWH3.
AI03441
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
DATA
TAR
SYNC
TAR
1
1
7
1
2
2
1
2
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