參數(shù)資料
型號(hào): M50FW080NB5TP
廠商: 意法半導(dǎo)體
英文描述: 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
中文描述: 8兆1兆× 8,統(tǒng)一座3V電源閃存固件集線器
文件頁(yè)數(shù): 43/56頁(yè)
文件大?。?/td> 292K
代理商: M50FW080NB5TP
M50FW080
DC and AC parameters
43/55
Figure 13.
A/A Mux interface Read AC waveforms
A/A Mux interface Read AC characteristics
AI03406
tAVAV
tCLAX
tCHAX
tGLQX
tGLQV
tGHQX
VALID
A0-A10
G
DQ0-DQ7
RC
tCHQV
tGHQZ
COLUMN ADDR VALID
W
RP
tPHAV
ROW ADDR VALID
NEXT ADDR VALID
tAVCL
tAVCH
Table 24.
Symbol
Parameter
Test Condition
Value
Unit
t
AVAV
Read Cycle Time
Min
250
ns
t
AVCL
Row Address Valid to RC Low
Min
50
ns
t
CLAX
RC Low to Row Address Transition
Min
50
ns
t
AVCH
Column Address Valid to RC high
Min
50
ns
t
CHAX
t
CHQV(1)
t
GLQV(1)
RC High to Column Address Transition
Min
50
ns
RC High to Output Valid
Max
150
ns
Output Enable Low to Output Valid
Max
50
ns
t
PHAV
RP High to Row Address Valid
Min
1
μ
s
t
GLQX
Output Enable Low to Output Transition
Min
0
ns
t
GHQZ
Output Enable High to Output Hi-Z
Max
50
ns
t
GHQX
Output Hold from Output Enable High
Min
0
ns
1.
G may be delayed up to t
CHQV
– t
GLQV
after the rising edge of RC without impact on t
CHQV
.
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