參數(shù)資料
型號: M52D128168A-7.5BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, FBGA-54
文件頁數(shù): 29/47頁
文件大小: 1209K
代理商: M52D128168A-7.5BG
ES MT
FUNCTION TRUTH TABLE (TABLE2)
Preliminary
M52D128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
29/47
Current
State
Self
Refresh
All
Banks
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
above
CKE
( n-1 )
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
L
L
CKE
n
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
H
L
H
L
CS RAS CAS
WE
X
X
H
X
L
H
L
H
L
H
L
L
X
X
X
X
H
X
L
H
L
H
L
H
L
L
X
X
X
X
H
X
L
H
L
H
L
H
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
ADDR
ACTION
Note
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
H
L
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA
X
X
INVALID
Exit Self Refresh
Idle after tRFC (ABI)
Exit Self Refresh
Idle after tRFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh
ABI
Exit Self Refresh
ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
NOP
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
6
6
7
7
8
8
8
9
9
OP Code
X
X
X
X
X
Abbreviations
:
ABI = All Banks Idle, RA = Row Address
*Note : 6.CKE low to high transition is asynchronous.
7.CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + t
SS
must be satisfy before any command other than exit.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
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