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參數(shù)資料
| 型號(hào)： | M52D128168A-7.5BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | 8 X 8 MM, LEAD FREE, FBGA-54 |
| 文件頁(yè)數(shù)： | 41/47頁(yè) |
| 文件大?。?/td> | 1209K |
| 代理商： | M52D128168A-7.5BG |
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ES MT
Preliminary
M52D128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
41/47
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of t
RDL
.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
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PDF描述 |
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| M52D128168A-7.5TG | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52D16161A | 512K x 16Bit x 2Banks Synchronous DRAM |
| M52D16161A-10BG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M52D16161A-10TG | 512K x 16Bit x 2Banks Synchronous DRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M52D128168A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Mobile Synchronous DRAM |
| M52D128168A-7TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Mobile Synchronous DRAM |
| M52D16161A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Mobile Synchronous DRAM |
| M52D16161A_09 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Mobile Synchronous DRAM |
| M52D16161A_1 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Mobile Synchronous DRAM |
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